Dear Srs.
I’m working in a board design for I/Q mod/demod baseband front-end ( that is 2 DACs and 2 ADC per board) in a multiple board configuration for a phased array application. A Tx/Rx sync (deterministic delay) inboard and intra board is a must. Baseband bandwidth of DC-1 GHz. The sampling frequency is around 2.500 Gbps. From your portfolio of components I plan to use the DAC39J82 at 1.250 Gbps with x2 interpolation and two ADC12J2700 (my first idea was to use the ADC32RF451 dual but if I understand correctly table 14 from the datasheet, not possible for JESD204B subclass 1).
Based on TI application note about synchronization of multiboard ADC12J4000 the idea is to use a 10 MHz matched length reference clock for each board as the OSCin for the LMK04828 in Single-Loop cascaded 0-Delay Mode with VCO0 to get the 2.500 GHz (x2 ADC), 1250 GHz (x1 dual DAC), suitable FPGA dev clock (x3 JESD204B subclass1 connections ) and SYSREF 10 MHz (x4 2ADC, 1 DAC and the FPGA). All will be always locked to the smallest freq (SYSREF) and always in sync (it is assumed that DEVCLK are a suitable multiple of SYSREF freq for the LMFS mode setting of the IC)
This is my first work with JESD204B and would like to check a few things:
1.- Are my assumptions correct about the general scheme and being the ADC32RF451 not suitable?
2.- Do I need an independent JESD204 connection in the Xilinx FPGA for each IC or I can group them (the ADCs for example)?
3.- Is it worth the dual loop nested-0 configuration for better phase noise and do you have an example for a working schematic.
4.- Which is the sync uncertainty between transmit and receive inboard and intraboard, 2.5GHz or 1.250GHz half clock period?
5.- Is the Xilinx JESD204B core compatible with this configuration?
Best regards
