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TR baseband Module syncrhonization

Other Parts Discussed in Thread: DAC39J82, ADC12J2700, LMK04828, ADC12J4000, ADC32RF45

Dear Srs.

I’m working in a board design for I/Q mod/demod baseband front-end ( that is 2 DACs and 2 ADC per board) in a multiple board configuration for a phased array application. A Tx/Rx sync (deterministic delay) inboard and intra board is a must. Baseband bandwidth of DC-1 GHz. The sampling frequency is  around 2.500 Gbps. From your portfolio of components I plan to use the DAC39J82 at 1.250 Gbps with x2 interpolation and two ADC12J2700 (my first idea was to use the ADC32RF451 dual but if I understand correctly table 14 from the datasheet, not possible for JESD204B subclass 1).

Based on TI application note about synchronization of multiboard ADC12J4000 the idea is to use a 10 MHz matched length reference clock for each board as the OSCin for the LMK04828 in Single-Loop cascaded 0-Delay Mode with VCO0 to get the 2.500 GHz (x2 ADC), 1250 GHz (x1 dual DAC), suitable FPGA dev clock (x3 JESD204B subclass1 connections ) and SYSREF 10 MHz (x4 2ADC, 1 DAC and the FPGA). All will be always locked to the smallest freq (SYSREF) and always in sync (it is assumed that DEVCLK are a suitable multiple of SYSREF freq for the LMFS mode setting of the IC)

This is my first work with JESD204B and would like to check a few things:

1.- Are my assumptions correct about the general scheme and being the ADC32RF451 not suitable?

2.- Do I need an independent JESD204 connection in the Xilinx FPGA for each IC or I can group them (the ADCs for example)?

3.- Is it worth the dual loop nested-0 configuration for better phase noise and do you have an example for a working schematic.

4.- Which is the sync uncertainty between transmit and receive inboard and intraboard, 2.5GHz or 1.250GHz half clock period?

5.- Is the Xilinx JESD204B core compatible with this configuration?

Best regards

  • Hi Juan

    The ADC32RF45 can be used in JESD204B subclass 1 in DDC Bypass mode at the following resolutions and maximum sample rates. All of the modes listed in Table 14 are Subclass 1. The JESD MODE values listed in the table are just the different register field settings required to configure the device into this mode of operation:

    Resolution (bits) Max Fclk (GHz) SERDES Ratio (Fserdes/Fclk)
    12 3 4
    14 2.46 5
    14 1.23 10

    Regarding your questions.

    1. Your general scheme seems OK.
    2. Each ADC device should have an independent JESD204B link with the FPGA. This is easiest to manage for link startup and error checking etc. There will be dedicated ~SYNC signals for each link.
    3. This question is best asked in the clocking forum monitored by the LMK04828 experts. Here is a link to that forum:
    4. I not sure I understand this question completely. Is this specifically addressing the LMK04828 capabilities, or the potential system performance?
    5. I believe you can implement multiple JESD204B cores to accomplish what is needed. The experts at Xilinx will be able to answer this best.

    Best regards,

    Jim B

  • Hi Jim,

    Thanks for the answers. I will check questiion 3 with the LMK04828 experts. The 4th question was related to the final coherence of the system. I understand at the end all the timing of the ADC/DAC is in sync with the same 2.5GHz pulse across all the boards.

    Finally, when is the  ADC32RF45 expected to be available?