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ADS1282: Multiplexed input with Read by command

Mahesh KC03
Intellectual 1360 points
Other Parts Discussed in Thread: ADS1282

Hi,

One of customers is using the ADS1282 in his design and needs to convert the input data at 2ksps. The inputs need to be selected alternatively; i.e. Ch1 alternated with Ch2. The data rate needs to maintained at 2Ksps.

I plan to use "Read data by command" as we need to change the input channel alternatively. I have attached the timing diagram for this application below.

 

I am trying to change the input Mux setting and issue RDATA before reading the data on DOUT in order to reduce the sample to sample delay. Is this sequence possible? Is it also possible to read out DOUT at the same time write to the device on DIN as DIN and DOUT are separate pins from the DSP? This will ensure that the read and config operation happens in parallel. The above scheme assumes that the "tdr" time is 1/Fdata rate which is given as the maximum value. What would be the minimum time after issuing RDATA and the DRDY going low?

If the above scheme is not possible (RDATA command before reading data), can we read the data first and then issue the RDATA command?

Is there a better solution for this?

  • 0
    TI__Mastermind 44680 points

    Hi Mahesh,

    In order to achieve the 2 kSPS data rate while MUX'ing, the ADS1282 will need to be operated at 16 kSPS (SINC filter mode) or faster, assuming that the clock is 4.096 MHz...

    In FIR filter mode, the digital filter requires 63 conversion cycles to settle.
    In SINC filter mode, the filter settles faster, but still requires several conversion cycles.

    Refer to tDR in table 10:

    At 16 kSPS, the time to data ready will be about 408 us. That leaves ~92 us to read the data and switch the MUX. Since this operation requires about 64 SCLKs, SCLK will need to be around 1 MHz to meet this timing requirement...going to 32 kSPS, will allow more time for this operation and allow for a slower SCLK frequency.

    Regarding the command sequence, the data must be read before writing to the device registers.
    The ADS1282 resets the digital filter and restarts conversions after writing to the device registers - it does not preserve the last conversion result.

     

    Best Regards,
    Chris

  • 0 in reply to Christopher Hall
    TI__Intellectual 1360 points

    Hi Chris,

    I have altered the timing diagram going through your suggestions. Please check if this will meet the target.

    The total SCLK cycles needed to fit in the 92us period is around 68. This can happen with a 1MHz SCLK.

    Since we are using only the Sinc filter which has lobes around the harmonics as well, what is its impact on the noise performance and ENOB? If we are running at 16ksps, the decimation ratio is pretty small around 64. What is it's effect on ENOB?

    When the DRDY signal goes low indicating the occurrence of new data, do we directly read it out from DOUT with the SCLK or do we need to send any command over DIN and then start?

    When the SYNC pin is unused as in this case, can it be tied low?

  • 0 in reply to Mahesh KC03
    TI__Mastermind 44680 points

    Hi Mahesh,

    A few comments:

    • The data read out is 32-bits (without a /CS, the readback cannot be truncated).
    • Do NOT send SCLKs during the delay! The device may see this as another command.

    The command sequence should look some like this:

    Mahesh KC03 said:
    Since we are using only the Sinc filter which has lobes around the harmonics as well, what is its impact on the noise performance and ENOB? If we are running at 16ksps, the decimation ratio is pretty small around 64. What is it's effect on ENOB?

    The noise performance won't be very good when using the SINC filter, because the high-frequency modulator noise will start to appear in the output result (this noise is normally filtered out when used with the FIR filter).

    Typically, the SINC filter on the ADS1282 is only used as a "pre-filter". For best performance, it should really be followed up with another post-processing digital filter to remove the modulator noise... However, this may added too much latency to your particular application.

     

    Mahesh KC03 said:
    When the DRDY signal goes low indicating the occurrence of new data, do we directly read it out from DOUT with the SCLK or do we need to send any command over DIN and then start?

    You should be able to read the data directly if the RDATA command was sent in the previous frame (before /DRDY went low).

     

    Mahesh KC03 said:
    When the SYNC pin is unused as in this case, can it be tied low?

    The device looks for a SYNC transition, so when it's unused you can tie the SYNC pin either high or low.

    Best Regards,
    Chris