Hi
I read ads54j66 high performance 4 channel TI's adc and i can not find some exact data like minimum conversion rate, performance change @ different sampling rates except power dissipation and of course related design files and packages for my schematic and pcb design verification. Also i'm confused with typical application section of ads54j66 datasheet that links each pair of JESD204 outputs and related Sync pins to separate FPGAs or maybe to separate FPGA banks. Is this type of connection required? And finally which input bandwidth can support this ADC and can i sample a high bandwidth dc-coupled input as large as 300 MHz with ads54j66?
Regards