Master Clock for FPGA on TSW1200 Board

My apologies - i typed up an answer that same day and sent it, but just now i noticed that my answer never got posted.  So i am trying again, and attaching what i tried to post last time:

Hi,

The TSW1200 uses the on-board crystal oscillator to create a 250MHz internal clock in the FPGA, which clocks the large banks of internal buffer memory. 250MHz was about the most we could get at that time with the Virtex4 in the middle speed grade for such large blocks of memory.

The clock from the ADC into the TSW1200 is then used to latch the data into the FPGA and then push the samples into a small asynchronous FIFO at up to 250 Msps per bank of FIFO. (The ADS5400 at 1Gsps needs to push four samples at a time.). After pushing into the small FIFO, the rest of the TSW1200 is synchronous. The 250MHz is used to pop the small FIFO and push the samples into the large banks of memory synchronously.

This architecture was largely due to the speed limitations of FPGAs a few years ago for large (at that time 1Mbit was large) memories.

The clock out from the ADS5400 could I think be used as 'master' clock for the FPGA, even with the reset. The resetting of the CLKOUT was done carefully to be sure that there are never any short cycles. The clock cycle always stretches if necessary. So state machines and other logic in the FPGA will still run safely. Of course, if the CLKOUT were to be used in a DLL or PLL or other circuit that has to 'lock' or settle out then the occasional long cycle might present a problem. Or if you use the CLKOUT for a counter to count time to any precision then you might have to account for an accumulation of possible 'lost time' over time.

So, depending on what you want to do with the FPGA, I think the CLKOUT can be used for most applications.

Regards,
Richard P