ADC32RF45 do not work

Hi,

who is your FAE who is supporting you and passing the configuration files to you?  That would help us identify the proper person on our end to support you.

Yes, the device is complicated and that complexity can make it difficult to use.  Having a mix of preproduction silicon and final silicon makes it that much more difficult due to the differences between the two revisions of silicon.

First off, if you are unable to read from a paged register, then that is almost always indicative of the ADC *not* seeing the sample clock or the SYSREF signal.   The device *must* have the sample clock running *and* the proper SYSREF running before the ADC can be configured.  if the clock or SYSREF are not proper, then the SPI readback will allow the non-paged Master registers to be read back but all the paged registers will read back zero.  so this would be the first thing that you would want to fix, because without the SPI port working for all five boards then nothing else is going to work.

Also, you need to be aware of the differences between preproduction silicon and final silicon.  The pre-production material has the common mode voltage requirement for SYSREF down around 0.6V.   This was changed to 1.2V for final silicon so that an LVDS driver can drive SYSREF.  But on pre-production material you will *need* to set up the SYSREF signal to be centered down around 0.6V.  Otherwise, the device will not see SYSREF and the device could not be configured.  On our EVM we had a resistive voltage divider on SYSREF to cut the common mode down by half, and when we install final silicon on that EVM we remove the voltage divider.  Also, preproduction material does not include the 100ohm termination for SYSREF on the silicon so the 100ohm would have to be external to the ADC.  Final silicon has the internal 100 ohm termination on SYSREF.  

Also, for preproduction material the polarity of SYNC is inverted compared to final silicon.  So your FPGA configuration will have to account for this.  And finally, the preproduction material will *only* support the 12bit 5-sample mode of LMFS82820.   It will not support the 14bit mode of LMFS 8224.  You need final silicon material for that.

And finally, the preproduction material *must* have a hardware reset before configuration.  The EVM has a push button for the hardware reset.  Until the reset pin of the device is toggled, the common mode biasing for the sample clock is not enabled and the device will not 'see' the sample clock.  final silicon material does not require the hardware reset.  Given all the differences between preproduction and final silicon, I might suggest focusing your efforts on final silicon.  But with the differences I just described it is possible to get both working.

Also, there is a minimum operating rate for the ADC32RF45, and 1.288Gsps is too slow for the device to reliably operate.   There will be an ADC32RF42 device to follow that will be rated for 1.5Gsps and below.  But ADC32RF45 is rated for 3 Gsps down to some minimum that I will have to find out from the design team.  I think the minimum may be somewhere around 1.4Gsps.    The differences in the config files that you noticed for different sample rate (registers D5 and D8) are the 'SLOW SPEED' enable bits, and the datasheet on the web identifies those bits are needed for operation below 1.75Gsps down to the minimum sample rate.  I sometimes see silicon operate at 1.288Gsps, but it is not guaranteed.  (and CMOS circuitry is usually affected by temperature, and I could not guarantee that the PLL is slower at high temp but it is possible)

Regards,

RIchard P.