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ADS1278 MSB inversion

smercer
Prodigy 30 points

Other Parts Discussed in Thread: ADS1278

I have a problem similar to the "ADS1278 bit inversion issue" posted April 27, 2010 to May 9, 2010.  However, when my problem occurs, bit 23 is inverted on all 8 channels but only at the zero crossings of the analog input data.  For example, three successive reads within the data could be -2 (0xFFFFFE) then -8388546 (0x80003E) then 73 (0x000049) but they should be -2 (0xFFFFFe) then 62 (0x00003E) then 73 (0x000049).  Another three successive reads could be 30 (0x00001E) then 8388527 (0x7FFFAF) then -114 (0xFFFF8e) but they should be 30 (0x00001E) then -81 (0xFFFFAF) then -114 (0xFFFF8E).  The rest of my data, positive or negative, is correct.

I'm using the ADS1278 frame-sync interface protocol and discrete data output mode.  My data rate is 100kSPS.

Do you have any suggestions?  Any help you may provide will be greatly appreciated.

 

  • TI__Mastermind 43915 points

    Hi smercer, 

    Can I have some more information about your system. First of all, what speed are you running your SCLK and FCLK at? If you are running fclk=sclk, try slowing sclk to see if it fixes the issue.

    Secondly, have you used a scope to probe the data signals to see what the ADC is outputting or just going off of what your controller reads back? 

    Regards,

    Tony Calabria 

  • in reply to Tony Calabria
    Prodigy 30 points

    Tony,

    CLK = 25.6MHz, SCLK = 12.8MHz and FSYNC = 100kHz when the problem occurs.  The problem does not occur when CLK = 12.8MHz, SCLK = 6.4MHz and FSYNC = 50kHz.  We've collected gigabytes of data at both sets of clock frequencies.  Even at the 100kHz sample rate, the problem does not always occur.  It probably occurs about 1% of the time.

    I've attached an example good record.  It seems I can only attach one file at a time so I'll post again with an example bad record.  Both records were collected at the 100kHz sample rate.  If you plot both examples you will quickly see the inverted sign bits.

    I've probed the clock signals to the ADC but not the ADC data outputs.

    Do you have any further suggestions?

    Thank you.

    Sandra Mercer

     

     

  • in reply to smercer
    Prodigy 30 points

    Tony,

    I've attached the example bad record.

    Regards,

    Sandra Mercer

     

  • in reply to smercer
    TI__Mastermind 43915 points

    Sandra, 

    The fact that when you divide the three system clocks in half the data reads out correctly hints that there may be a hold time or propagation delay spec that is not being met at the faster speeds. In the past, we have seen customers have read back problems because they were not meeting hold time specs, they were reading the data on the wrong edge of sclk, etc. So a couple things to check - 

    - Are you reading on the Falling edge of sclk. This part uses the falling edge as the critical edge. 

    - Verify that you are meeting the tMSBPD propagation delay spec. If you scope picture of the SCLK and FSYNC signals match the data sheet and you are reading on the Falling edge of sclk, you should meet this spec with a 12MHz sclk. If you are reading on the rising edge of sclk you may have a problem. 

    - Is your FSYNC rising and falling on the falling edge of sclk as shown in the data sheet? 

    Also, you may want to probe the sclk and dout to see if the data is MSB of the data is changing at all (maybe it is changing after the clock edge and your micro-controller is missing the read) or if the MSB is not changing at all. 

    -Tony