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Rx FIFO errors in DAC37J82

Mark Michael
Prodigy 110 points

Other Parts Discussed in Thread: DAC37J82, DAC38J84

I am using the DAC37J82 with LMFS = 2221. I am using lanes 3 and 2 (setting 0x4A to 0x0C21), with continuous SYSREF and skipping 2 sysrefs then using all (0x5C to 0x0006). However, when I generate JESD data from the FPGA I get the following ALARM values and there is no output from the DAC:

0x64 - 0xFF0E (Dont use lane 0)
0x65 - 0xFF0B (Dont use lane 1)
0x66 - 0x0002 (FIFO errors on lane 2)
0x67 - 0x0002 (FIFO errors on lane 3)
0x68 - 0xFF0D (Dont use lane 4)
0x69 - 0xFF08 (Dont use lane 5)
0x6A - 0xFD0E (Dont use lane 6)
0x6B - 0xFE0A (Dont use lane 7)
0x6C - 0x0007  (seems good, SERDES PLL is locking and I dont use the DAC PLL)
0x6D - 0x0070 (not sure why this isnt 0x00F3)
Is there a suggestion to debug this?
I set my register settings in the following order (address with the value in the comments)
        7'h24, // 0x0000 Disarm SYSREF
        7'h5C, // 0x0000 Disarm iniitalization circuit

        7'h1A, // 0x0023 DAC_PLL in sleep mode, DAC_C and DAC_D in sleep mode
        7'h31, // 0x1000 Assert pll_reset
        7'h32, // 0x0000 VCO stuff unused
        7'h33, // 0x0000 VCO stuff unused

        7'h3B, // 0x0800 Divide by 2 for SERDES PLL reference, choose DAC PLL (#WEIRD)
        7'h3C, // 0x0228 Medium loop bandwidth, high VCO, MPY settings is 0x04
        7'h3C, // 0x0028 Medium loop bandwidth, low VCO, MPY settings is 0x04  
        7'h3D, // 0x0088 Enable SERDES equalizer and offset compensation
        7'h3E, // 0x0148 AC Termination, quarter rate (1 sample per SERDES PLL), buswidth 3'b010

        7'h3F, // 0x005A Invert p/n as in my schematic
        7'h46, // 0x1882 Change JESD lane IDs 0 -> 3 1 -> 2 2 -> 1
        7'h47, // 0x01C8 Change JESD lane IDs 3 -> 0 4 -> 7 5 -> 4
        7'h48, // 0x3143 Change JESD lane IDs 6 -> 6 7 -> 5
        7'h49, // 0x0000 All lanes in link 0
        7'h4A, // 0x0C3E Turns on lanes 2 and 3, dual dac mode, reset JESD**
        7'h60, // 0x4567 Keep lane numbers as they are
        7'h61, // 0x0111 Only use link 0 for generating SYNC signals

        7'h22, // 0x1B1B Sample paths from JESD to outputs
        7'h23, // 0x01FF Allow everything to sleep
        7'h24, // 0x0020 Use only next SYSREF PULSE
        7'h25, // 0x6000 Divide DACCLK by 8

        7'h00, // 0x0418 8x interpolation no QMC, summing channels, or sinc filters
        7'h01, // 0x0003 No delays or compliments to outputs
        7'h02, // 0x2002 Zero data when no JESD, 3 wire SPI, 2's compliment
        7'h03, // 0xA300 Coarse gain, FIFO erros 0 dont data, tx not enabled
        7'h04, // 0xF3F3 FIFO and lane alarms enables lanes 2 and 3
        7'h05, // 0xFFF7 only allow Serdes block 0 PLL lock alarm
        7'h06, // 0xFFFF Jesd test alarms
        7'h4A, // 0x0C3E Turns on lanes 2 and 3, dual dac mode, reset JESD**
        7'h4B, // 0x0801 Use F value of 2 and elastic buffers of 8
        7'h4C, // 0x0901 Use K value of 10 and L value of 2
        7'h4D, // 0x0100 Use M value of 2 and S value of 1
        7'h4E, // 0x0F0F Turn off scrambler and HD
        7'h4F, // 0x1C61 Dont match a specfic character for buffering
        7'h51, // 0x00DC Which errors cause SYNC request, Link 0
        7'h52, // 0x00FF Error counter mask
        7'h54, // 0x00FC Which errors cause sync request, Link 1
        7'h55, // 0x00FF Error counter mask
        7'h57, // 0x00FF Which errors cause sync request, Link 2
        7'h58, // 0x00FF Error counters mask
        7'h5A, // 0x00FF Which errors cause sync request, Link 3
        7'h5B, // 0x00FF Error counters mask
        7'h5C, // 0x0006 Skip two SYSREFs then use all
        7'h5F, // 0x3210 Change lane numbers
        7'h60, // 0x5764 Change lane numbers
        7'h61, // 0x0211 Set the SYNC_N* values
        7'h6C, // 0x0000 Clear PLL alarms

        7'h1E, // 0x9999 Select SYNC source for QMC (just from SPI)
        7'h1F, // 0x9980 Select SYNC source for mixers and NCO (just from SPI)
        7'h20  // 0x8008 Select SYNC source for dither and for FIR (just from SPI)
Then I ensure that 0x6c indicates that SERDES is locked then I program 0x6C to 0x0C3F and then program it again to 0x0C21. After that is complete I start transmitting from the FPGAs JESD module and I check alarms every few milliseconds after that.
Any help would be appreciated
  • 0
    Prodigy 110 points

    A little more information... I have a 1228.8 MHz DACCLK (which I can probe with a scope and see the first harmonic). My SYSREF is 15.36MHz, I can probe this and it looks fine. I am trying to do 8x interpolation, with 153.6MSPS (153.6*16bits*10/8 = 3072Mbps) and I use 2 lanes each going at 3072Mbps.

    To start JESD, I program register 0x4A to 0x0C3F then program it again to 0x0C21. I do this while the FPGA is still not transmitting anything. I take the FPGA's JESD transmitter out of reset once this step has been completed.


    Again, any help is appreciated.

  • 0
    TI__Guru* 83405 points
    Mark,

    It may take a while to analyze some of the information here. One thing I recommend is to use our DAC38J84 EVM GUI to configure the DAC the way you intended, and then double check the registers on the low level page to cross-check your settings.

    Also, I did not see the status for the LVDS SYNCB level. The LVDS SYNCB should be in logic high by default, and the pulled to logic low through JESD INIT process (along with SYSREF pulse) to request K characters from the FPGA. If the FPGA never sends K character, then the link cannot be established.

    Please check the status of the LVDS SYNCB level with each step to see if there are any transitions.

    -Kang
  • 0 in reply to Kang Hsia
    Prodigy 110 points
    Hi Kang,

    Thanks for getting back to me. I generated these settings by copying the EVM GUI configurations and making slight adjustments to things like the polarity of the RX pins. Since I originally posted this message I have changed the lane id's and the rx lanes to use (I now use lanes 0 and lanes 1, instead of 2 and 3).

    The SYNC pin goes low upon programming of register 0x4A to 0x0321. After this I clear all the alarm registers and then wait a few milliseconds and read the alarm registers. There are no transitions after that.

    At this point the JESD204B IP core is still in reset on the FPGA, should I have it out of reset at this stage so it can catch the transition?

    Mark
  • 0 in reply to Mark Michael
    Prodigy 110 points

    Sorry, I hadn't connected the sync_n pin correctly to the JESD204B core. Now the SYNCB pin does the following:

    Transitions from high to low upon programming 0x4A to 0x0321
    Transitions from low to high after the JESD204B IP core is out of reset by about 200 clock cylces of the management clock (100MHz)
    Transitions from high to low about 200 clock cycles from the previous transition
    Transitions from low to high after about 150 clock cycles
    Stays high from there on out.

    The alarm values are still the same (0x0002 for the lanes that I am using, registers 0x64 and 0x65, 0x0070 for register 0x6D, 0x0007 for register 0x6C).

  • 0 in reply to Mark Michael
    Prodigy 110 points

    Update: I changed the 0x5C register to 0x8888 (doesn't use SYSREF on any of the links) but still sent the SYSREF signal to the FPGA IP core. Now the DAC outputs the values I expect (I doubt they are synchronized between each other).  However, I still get the RX fifo alarms (registers 0x64 and 0x65 are both 0x0002).

    I guess my remaining questions are:
            1) should I be concerned with these RX FIFO errors and, if so, what does that mean?
            2) How do I get everything to work using the SYSREF? Could FPGA delays between the device clock and the SYSREF signal be causing this problem? Are there timing constraints I should put to make sure these things go away?

    In terms of SYNCB pin, after transitioning from low to high it is a little unstable for about 3us (300 cycles of 100MHz clock) and then it goes high and remains high for the rest of the experiment. I attached a sample signal tap output of this file jesd_sync_n is directly connected to the SYNCB pin from the DAC. jesd_ctrl_rdy goes high after the the transceiver controller successfully comes out of reset.

  • 0 in reply to Kang Hsia
    Prodigy 110 points
    Hi Kang,

    Could I please get a response? I have yet to be able to remove the Rx FIFO errors. Is there some sort of debugging procedure to figure out these issues? I performed tests like outputting a sine wave or a ramp function and the DAC outputs as expected, but if I try to use the coarse mixer (program register 0x2 to 0x2042 and 0x0D to 0x4400) I get an incorrect output (mainly just noise added to my original signal). Also if I set register 0x03 to 0xF380, which 0s data on SerDes FIFO errors, I get no output.

    Other notes, SYNCB pin is always high once the link is established. I have resolved my SYSREF issues by added timing constraints and now I have SYSREF always on and I use every SYSREF pulse on the DAC (there are no errors associated with this since SYNCB remains high and I periodically poll the alarm registers.

    Thanks,

    Mark