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Pausing the clock to ADC128S102 during Hold mode

Other Parts Discussed in Thread: ADC128S102

I am planning to use an 8-bit SPI master to interface with the ADC128S102. This means that there will be pause in the clock after the first 8-bits. Will this affect the conversion process and the result? The chip select will be held low for the entire 16-bits but I'm worried if the charge in the sampling capacitor can be converted accurately with the pause in the clock. The pause could be around 20 usec.