hi!
I'm trying to develop an algorithm for the ads7865 using vhdl, i used a state machine for the implementation of the algorithm and it's divided like this:
Wait state: CS high, input signals ignored and 3-state outputs
CONVST high conversion doesn't start
RD high, synchronization doesn't start
Adq_data: CS down to 0,adc enabled, normal operation
WR low, parellel interface doesn't read data
data present on input are storage on the fpga
3 clock pulses are required for this state
Conv_data: CONVST low
fpga reads high busy and start counting 13 clock cycles
next state is wait state
Write_ref: WR high for write in conf register
GPIO_1(21) <= '0'; -- R1
GPIO_1(20) <= '1'; -- R0
GPIO_1(14) <= '0'; -- A2
GPIO_1(13) <= '0'; -- A1
GPIO_1(12) <= '1'; -- A0
GPIO_3(11) <= '1'; -- second pulse of write for enter data
GPIO_1(23) <= '0'; -- DB11
GPIO_1(22) <= '0'; -- DB10
GPIO_1(21 downto 12) <= "1111111111";
state <= WAIT_STATE;
Channel_select:
when "00" => -- Channel 0
GPIO_1(23) <= '0'; --c1 of the ADC register
GPIO_1(22) <= '0'; --c0 of the ADC register
when "11" => -- Channel 1
GPIO_1(23) <= '1';
GPIO_1(22) <= '1';
But i'm not sure if the only thing i need to do for channel selection is write c1 and c0 on the configuration register, and i don't how if i need another state for read data.
