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ADS8860 : CONVST signal

Other Parts Discussed in Thread: ADS8860

I need to interface ADS8860 with an FPGA using SPI - 3 wire operation.

According to the timing diagram, the CONVST pin must not be held high more than 710ns. I would like to know whether holding it longer will produce incorrect results.

As far as I understood, the CONVST pin holds the data as long as it is high and starts conversion process at the falling edge of the CONVST signal. In principle, holding the CONVST pin high for a longer time than 710ns should only hold the input data longer.

Have I understood the concept correctly? 

Thanks

Tobie

  • Hi Tobie,

    The 710ns refers to the maximum ADC conversion time; but it is not a maximum pulse duration requirement for the CONVST signal.  The CONVST rising edge triggers the conversion.  At the rising edge of CONVST, the acquisition period ends, the signal is sampled and the conversion period starts. The CONVST can be brought low after the maximum conversion time (710ns) lapses.    Please refer to Figure 49 and page 20 of the datasheet for 3-wire operation.

    On 3-Wire CS Mode without BUSY indicator (DIN=1), a CONVST rising edge forces DOUT to 3-state, samples the input signal, and causes the device to enter the conversion phase. Conversion is done with the internal clock and continues regardless of the state of CONVST.  CONVST must return high before the minimum conversion time (tconv-min) elapses and is held high until the maximum possible conversion time (tconv-max) elapses. A high level on CONVST at the end of the conversion ensures the device does not generate a busy indicator.  CONVST, functioning as CS, can be brought low after the maximum conversion time (710ns) elapses.  On the CONVST falling edge, DOUT comes out of 3-state and the device outputs the MSB of data.

    Thanks and Best Regards,

    Luis

  • Luis

    Thank you for the fast and explanatory reply. The answer is very helpful.

    Regards
    Tobie