Hi,
We simulated the ADC input circuit along with impedance matching circuit which is referred from ADC16DV160 evaluation board schematic result was found to be
approximately same for both return loss and insertion loss.(refer TI evaluation board schematic result and our design result)
As per design the insertion loss of the ADC at 30MHz is very poor(-26.28) and we consider the input impedance of the ADC circuit is 71.088 -j*1182 @ 30MHz
(Impedance value is taken from SnP file). Some modification has been done in our schematic(Refer Design_30MHz_term_schematic)
ADC Part : ADC16DV160
Input frequency range is 10 to 40 Mhz.
Return loss is obtained -17.625dB (refer simulation result)
Insertion loss is obtained -26.28dB (refer simulation result).
Questions:
1. Kindly recommend the RF front end circuit to be designed for getting best insertion loss at 30MHz for our design.(Expected result is below -4dB)
Attached file
1. TI_Evaluation board schematic_S1P file_@30MHz - Evaluation board schematic simulated @30MHz based on the SnP file
2. TI_Evaluation board schematic result__S1P file_@30MHz - Evaluation board schematic result based on the Snp file
3. TI_Evaluation board schematic_Termination_@30MHz - Evaluation board schematic simulated @30MHz based on the equivalent termination resistor (71.088- j*1182) @ 30MHz find out the insertion loss
4. TI_Evaluation board schematic result_Termination_@30MHz- Evaluation board schematic result based on the Snp file
5. Design_30MHz_Term_Schematic
6. Design_30MHz_Term_Result
TI_Evaluation board schematic result__S1P file_@30MHz.pdfTI_Evaluation board schematic result_Termination_@30MHz.pdfTI_Evaluation board schematic_S1P file_@30MHz.pdfTI_Evaluation board schematic_Termination_@30MHz.pdfDesign_30MHz_Term_Schematic.pdfDesign_30MHz_Term_Result.pdf
