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JESD204B Interface: Hardware necessaries

Moham
Intellectual 635 points
Other Parts Discussed in Thread: ADS54J66, ADS54J66EVM, LMK04828

Hi,

I'm designing a sampling board with JESD204B interface ADC named ADS54J66. Clockoing this device and related FPGA needs at least a clock distributor and also a sysref generator/distributor at a glance. Is this true and which other hardware necessaries are required? Which requirements are highlight for clocking, sysref gen., interfacing and acceptable performance except board design considerations?

Regards

  • 0
    TI__Guru* 91947 points

    Moham,

    If you plan on running in subclass 1 mode, you will need a device clock and SYSREF that are source synchronized. The capture device will also need these two clocks as well and all of them synchronized. You will also have a SYNC interface between the FPGA and the ADS54J66, I have attached a copy of the ADS54J66EVM schematic for reference. The LMK04828 provides the required device clock and SYSREF for both devices when using the ADS54J66EVM with the TSW14J56EVM, which contains the FPGA used for the interface.

    Regards,

    Jim

     ADS54J66_ADS58J63_ADS58J66-SCH_A.pdf

  • 0 in reply to jim s
    Intellectual 635 points
    Jim,

    Thanks a lot but i have not an access to your schematic link and can not download it. Please share with another way if it's possible for you. Next, it's necessary using LMK04828 as your propose but in compare with other TI clock distribution networks have lower performance specifications particularly in additive jitter. Is it sufficient for a JESD204B Interface ADC with high interface rate about 10Gbps? Assuming perfect Phase noise clock source and using only distribution network not using PLL can better this performance?

    Regards
  • 0 in reply to Moham
    TI__Guru* 91947 points

    Moham,

    See if you can download the files from the following link below. I am confused by your other question. Are you asking for a part with less performance than the LMK04828 or one with better performance? The JESD204B output rate does not matter as much when looking at jitter numbers. The jitter spec comes in to play when looking at the analog performance such as SNR and SFDR of the device. If you use the LMK in clock distribution mode, the output performance will be better if your input source is cleaner than the internal PLL.

    Regards,

    Jim

  • 0 in reply to jim s
    Intellectual 635 points
    Jim,

    Thanks, but i think a serial link without transferring clock is very sensitive to generator clock jitter but no in scale of sample and hold sensitivity. So, your answer means using LMK04828 is necessary for having sync. SYSREF and CLK signals simultaneously? Finally Thank you very much for your file sharing.

    Thanks