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ADS1298 : Internal Test Signal Result's Conflict

muhammad ather
Intellectual 310 points
Other Parts Discussed in Thread: ADS1298

Hi,

I am using ADS1298 with a development kit having android running on it.  I am interfacing ADS1298 with the kit through SPI connections on J3. I ma using only three channels. CH1,CH2 and CH3, Channel's Mux is set to internal test signals. Here is some screen shots that shows my register settings and outputs :both while using Evaluation board and and while using kit.

Kit's Output

Register Settings

 EVM's Output

As it is seen, with data rate = 4000SPS and acquiring 4000 Samples/Channel , I get only one pulse with EVM and Multiple pulses with the kit. Can anyone help why is this happening ? 

Register configurations are same in both cases. Difference is the SCLK frequency. With kit SCLK is 1 MHz and with EVM the clock is approx 15 MHz.

  • 0
    TI__Mastermind 38745 points
    Hey Muhammad,

    Are you collecting a data point with every single DRDY signal? Are you sure you're only collecting 4000 samples? The test signal has a frequency of 1 Hz so the EVM scope shows the appropriate results.

    Regards,
    Brian Pisani
  • 0 in reply to Brian Pisani
    Intellectual 310 points

    Thanks Brian,

    You are always been helpful. I am very grateful to you for that. 

    I was debugging my code and hardware issues to overcome this problem. I am following the flow chart that is provided in the data sheet for test signals (at page 85) . I reached a the point where set START = 1. I am using opcode to start the communication and START pin is tied to ground. At that point in comments it is mentioned that DRDY will toggle at fclk/4096. I have checked it on oscilloscope. It is toggling but I have a doubt. I believe that it should remain high and after the specified time , it should toggle to low. I read data on every DRDY low signal. In my case DRDY is behaving oppositely. Screen shot is provided below.

    Please correct me if I am wrong.

     

    As seen the frequency of the signal is 500 Hz which is same as fclk/4096 ( fclk = 2.048 MHz ).  

    Another problem is that In my GUI I am unable to see last three registers. What will be their configurations ?

  • 0 in reply to muhammad ather
    Intellectual 310 points

    While using the the board with the EVM , DRDY is performing properly as shown below.

    Where am I wrong ?

  • 0 in reply to muhammad ather
    TI__Mastermind 38745 points

    Muhammad,

    DRDY will fall low when new data is available. It only comes back high under two conditions:

    1. SCLK toggles from high to low. Essentially if you talk to the part after DRDY transitions low, the signal will return high.
    2. No communication occured but new data is about to be available. DRDY will transition high briefly before falling low again to indicate new data is ready.

    The differences in your communication versus the EVM is that yours looks like case 2 and the EVM looks like case 1. In the image you show, the host is not communicating with the ADS1298.

    All of the registers you mentioned should power on as 0x00.

    Regards,

    Brian