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DAC3482 sync

user1218831
Prodigy 20 points
Other Parts Discussed in Thread: DAC3482, CDCE62005

Hello  

I'm debugging with DAC3482.   Now, It occured collision and 1away and 2away.

I'm reading SLAA584.

DACCLK_p/n  from CDCE62005 at  250MHz

DATACLK from FPGA at 250MHz

FrameCLK from FPGA at  15.625MHz ( =250MHz/16)

OSTR_p/n and SYNC_p/n are unconnected.

Interpolation = 4x

FIFO = on

NCO = on

fout = 140MHz

FIFO offset = 4 ( 0 to 7  with collision)

fvco = 4GHz

N = 1/16

P = 4

M = 64

FIFO sync   in=FRAME  out=OSTR

dataDLY and clkDLY = 0 to7 with collision

{ 0x00, 0x02, 0x9E } // Interpolation=4x FIFO on

,{ 0x01, 0x00, 0x0E } // normal
,{ 0x02, 0x80, 0x52 } // NCO on
,{ 0x03, 0xA0, 0x00 }
,{ 0x07, 0xD8, 0xFF }
,{ 0x08, 0x00, 0x00 }
,{ 0x09, 0x80, 0x00 } //FIFO offset=4
,{ 0x0C, 0x04, 0x00 }
,{ 0x0D, 0x44, 0x00 }
,{ 0x10, 0x00, 0x00 }
,{ 0x12, 0x00, 0x00 }
,{ 0x14, 0x0A, 0x3D }
,{ 0x15, 0x23, 0xD7 }
,{ 0x18, 0x2C, 0x67 } // PLL_P=4
,{ 0x19, 0x40, 0xF4 } // PLL_M=64 PLL_N=16
,{ 0x1A, 0xFC, 0x00 }
,{ 0x1B, 0x88, 0x00 }
,{ 0x1E, 0x91, 0x91 }
,{ 0x1F, 0x21, 0x20 } // syncsel datafomatter=FRAME
,{ 0x20, 0x24, 0x01 } // FIFO in_frame out_OSTR
,{ 0x24, 0x00, 0x00 } // dataDLY=111 clk_DLY=0_00

wait 100ms

{ 0x05, 0x00, 0x00 }
,{ 0x1F, 0x21, 0x20 }
,{ 0x00, 0x02, 0x9A } // Interpolation=4x FIFO on

,{ 0x1F, 0x81, 0x18 } // syncsel datafomatter=FRAME
,{ 0x20, 0x00, 0x00 } // FIFO sync disable
,{ 0x18, 0x24, 0x67 } // PLL_P=4 PLLon

,{ 0x85, 0xFF, 0xFF } // 0x05 read          ->  read data is 16'h3840
,{ 0x98, 0x55, 0x55 } // 0x18 read          ->  read data is 16'h2464
,{ 0x84, 0xFF, 0xFF } // 0x04 read          ->  read data is 16'hFEFF

Am i missing something here?

  • 0
    TI__Guru* 78324 points
    In single sync source mode, both FIFO input and FIFO output need to be initialized by the FRAME Signal (i.e. 0x20 = 0x2201).
    Also, single source mode requires FIFO optimization. See section 2.3 of the SLAA584 for detail.

    -Kang
  • 0 in reply to Kang Hsia
    Prodigy 20 points
    Thank you, Kang san.

    I changed the setting { 0x20, 0x22, 0x01 } // FIFO in_frame out_frame

    but read_data is 16'h3A40 ( address 0x05 ) by dacclk and dataclk are syncronized.
    Then DAC_out spectrum becomes every PFD frequency like a mountain.
    A mountain becomes like a hedgehog when I put CW signal.
    ( This result does not have a change than the last time )

    I mean FiFo-out clk needs same frequencies fifo_in clk. So I set fifo_in is FRAME, and FIFO_out is PFD by PLL_on (Figure6 SLAA584).
    Is This dual sync_mode?

    best regards.
    Ken