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AD32RF45 JESD Interface issue with KC705

Hi all,

Iam using AD32RF45 EVM with KC705 Xilinx EVM board to take the ADC Data through JESD interface(LMFS 8821, K=16,DDC=8,fs = 2457.6Gsps).
The initial K28.5 (BC-pattern) is received in FPGA and the FPGA is giving SYNC-high,even then the data is always BCs, actual data is not sent.
FPGA side the SYNCBP/N(differential) lines are LVDS 2.5V. Am I missing something here?

 

With Regards,

Divya P.

  • Hi,

    Check the polarity of the SYNC signal carefully.  If possible, try inverting the polarity of your SYNC signal.   If the FPGA is driving the SYNC with inverse polarity to what the ADC wants to see, then when the FPGA is de-asserting SYNC it becomes the polarity that the ADC sees as meaning output K28.5, and will stick in this state.  Also, there is a bit in the register space of the ADC to invert the SYNC polarity.

    At one point earlier in the development cycle we had the SYNC polarity invert from what it is now, and since we had already developed the files for our FPGA capture card we used the config file to invert the polarity of SYNC in the ADC after that to match that from our FPGA.  If you used our SPI GUI config files into the EVM, and your FPGA code was not written to expect to see an inverted SYNC, and then there would be a mismatch.

    The line in the config file that would be causing the problem would be:

    0x0058 0x20     // SYNC polarity inverted as the hsdcpro.ini inverts the sync

    Edit out this line, or change SYNC polarity from your FPGA.  Let me know if that turns out to be the issue.

    Regards,

    Richard P.

  • Hi Richard,

    Thanks for your reply.

    I have verified with SYNC polarity inverted and non_inverted (0x0058 0x20, 0x0058 0x00 resp), but the behavior is same.  I am using your SPI GUI to configure ADC. Do I need to take care anything in the hardware side, because irrespective of the SYNC it is giving the same.

    Regards,

    Divya P.

  • Hi Richard,

       I am able to take the ADC data into KC705, it was some ADC configuration issue. Thank you for looking into the issue