Hi all,
Iam using AD32RF45 EVM with KC705 Xilinx EVM board to take the ADC Data through JESD interface(LMFS 8821, K=16,DDC=8,fs = 2457.6Gsps).
The initial K28.5 (BC-pattern) is received in FPGA and the FPGA is giving SYNC-high,even then the data is always BCs, actual data is not sent.
FPGA side the SYNCBP/N(differential) lines are LVDS 2.5V. Am I missing something here?
With Regards,
Divya P.