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Power consumption ADS7809 or ADS8509

Other Parts Discussed in Thread: ADS8509, ADS7809

Hey y'all,

My name is Terra and I am an R&D Engineer at Los Alamos National Labradors. 

I'm combing through some datasheets for the ADS7809 and its immediate succesor the ADS8509. Overall solid datasheet. However, I am having issues figuring out what the maximum power/ current draw on the "VANA" pin is (i.e. how much power/ current does the analog supply draw. TI gives typical current draw on the analog at 100 kHz, and the maximum total draw of both the digital and analog cores combined, both good stats, but our analog core and digital core are powered by two supplies. The regulator providing the ADC analog supply can only put out 20 mA, hence the concern for just the analog's maximum current draw. Furthermore, our sample rate is much lower than 100 kHz and operates at a temperature lower than the maximum operating temperature of the part, so it would be nice to know maximum power draw as a function of temperature and sampling frequency. I've looked for a simulation of this part for TINA, LTSPICE, and PSPICE, but alas to not avail, but it really is only this aspect of the part that is of concern.

Any help is mega appreciated.

Thanks,
Terra 

  • Hello Terra

    Unfortunately we do not have the exact information.
    But at Fs= 250kHz, the current consumption on Vana is typically about 10 mA. Also from Figure 21, supply current vs temperature, the overall supply current is shown (both digital and analog) which maxes out at 16 mA. Thus, Vana's max would be lower than that. If you are using the device at a lower sampling frequency and lower temperature, than the overall power consumption would decrease.
    The 20mA regulator should suffice for the Vana pin. If you have other components on this same power rail though I would suggest changing the regulator to increase your margin.

    Thank you
    Cynthia
  • Hi Cynthia,

    Thanks for the response. I didn't notice figure 21 so it's great that you pointed it out and it helps. So the larger context of this question is that we are trying hard to avoid replacing the aforementioned regulator because it's low noise properties are favorable and we've used it in other designs. Then the other part of the context of the question which is that we want to use part in space. The guidelines we have for our parts include a certain added margin so that we increase the reliability of the part. We call the margin a derating factor, which I think is a common term. The way our derating factors work out is that a 20 mA regulator "derates" to 16 mA or in other words we need to include 4 mA of margin. So under typical circumstances we're okay 10 mA is plenty of margin. The worry I have is that 100 mW max power number between both Vana and Vdig. What proportion of that 100 mW power number goes to Vana and what proportion goes to Vdig. And as you mentioned, all these numbers come from a measurement where the sampling rate was 250 kHz. Does reducing the sample rate to 1 kHz reduce the power 250 fold? 100 fold? 2 fold? Does it have any significant effect?

    Thank you,
    Terra

  • Terra,

    Unfortunately, we do not have all the necessary information to give you exact numbers.

    The correlation between current consumption and power dissipation can be assumed to be linear, the analog side consumes about 2/3 of the total current consumption, thus it is likely that 2/3 of the 100mW power is from the analog side as well.

    As for the frequency decrease, in classic SAR ADCs, the correlation between sample rate and power is linear.  For example, if you are using a sampling frequency of 100 KHz and the power consumption is rated at 250KHZ, then the power consumption would also decrease by a factor of 2.5.  Note, to have the most accurate estimate the power consumption of the quiescent current would still need to be added, this though would be very minimal.

    Hope this helps, Cynthia