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ADS8353 Serial interface timing

masahiko shimizu
Guru 11235 points
Other Parts Discussed in Thread: ADS8353

Hi,

My customer is using ADS8353.
ADS8353 is operated with MSP430.

Customer has a question about Serial interface timing.

ADS8353 data width is 16bit.
But MSP430 data width is 8 bit, then MSP430 need to reciave data 2 times from A/D .
For the reason, Serial interface waveform is below.
There is a time between 8bits SCLK and 8bits SCLK.
Is it problem the following timing?

Best regards,
Shimizu

  • 0
    Guru 11235 points
    Hi,

    How is the progress?

    Best regards,
    Shimizu
  • 0 in reply to masahiko shimizu
    TI__Expert 4405 points

    Shimizu-san,

    I apologize for this delay in responding.

    The ADS8353 will be able to output its 16-bit data across multiple 8bit MSP430 frames as long as the CS is maintained low between frames (as you have correctly shown in the diagram).

    However, as mentioned in Table 6 of the datasheet the ADS8353 only supports 32-CLK mode. The customer will need to drive four 8-bit frames from the MSP430 with the CS contiunously held low. As shown in Figure 91, the data is launched on the 16th to 31st fall edge. The tCONV and tCLK timing specifications, listed in Table 13, need to be met to ensure performance.

    Regards,

    Sandeep