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ADS1255

Andy Rawkins
Prodigy 10 points

Other Parts Discussed in Thread: ADS1255

ADS1255 CLK 7.68Mhz

D0/CLK out 7.68Mhz

Using D0/CLK out of the ADS1255 to drive a MSP430.

Mode: Continuously converting

 

D0/CLK out is producing RFI in the shipping band with a strong peak at

161.2968Mhz 52dbuv

 

Problem has been tracked to D0/CLK out using a near field probe.

 

Have now inserted a R80 100R in series with D0 and MSP430 and shortened track length will this be enough to eradicate any RFI ? (yet to be tested)

Track length 17.6mm width 0.25mm

2141-024-cd-g Front End.pdf

  • 0
    TI__Mastermind 44780 points

    Hi Andy,

    Welcome to the TI E2E Forums;

    Adding a series resistor (or shunt capacitor) to the clock signal can certainly help...This slows down the clock edges and attenuates the higher frequency harmonics of the clock signal. Since you are seeing the 20th harmonic of the 7.68 MHz, I would think that adding 100 Ohms would be very effective; however, whether or not that will completely solve the problem, is difficult to say.

    In addition to attenuating the source of the RFI, consider the coupling mechanism(s) that caused the signal to radiate in the first place. Shorting the track length of the clock signal is a good idea. Also, look at the PCB grounding...

    • Make sure the clock trace is routed directly over a ground plane to keep the clock circuit's loop area small.
    • Avoid ground plane splits/gaps whenever possible; if a ground plane splits exist, don't route traces across the split.

    There are many other PCB layout techniques and guidelines that can help. Here are a couple of resources that I would recommend:

     

    Best Regards,
    Chris