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What is the lowest latency ADC/DAC/DSP solution? (goal less than 1 ns total latency for ADC+DAC+DSP,)

Other Parts Discussed in Thread: ADC12D800RF, 66AK2L06, ADS5400

We are running into difficulty identifying low latency ADC (and DAC and DSP) for our design.  End-to-end overall latency is a key design goal.  For example, even though the  ADC12D800RF has approx. 1 GHz sample rate, it has about 20 ns delay/latency and is much too large/slow for our application.

What is the lowest latency ADC/DAC/DSP solution? 

our design goal is  less than 1 ns total latency for ADC+DAC+DSP, but would like to hear opinions even as low as 10 ns latency.  

we guess that the 66AK2L06 Evaluation Module is a good start, but are less sure what ADC and DAC evaluation modules may be compatible and may have under 1ns latency (including any pipeline delays).  we may need to go much higher than 1 GHz sampling, if there are pipelines in the ADC or DAC.

our preference is to build a prototype using evaluation boards

Some ballpark goals/needs for the system are:

1) >1Gsample/s,  >9 bits, ADC  with conversion latency <250 ps including any pipeline delays, etc
2) >1Gsample/s,  >9 bits, DAC  with conversion latency <250 ps including any pipeline delays, etc
3) DSP core capable of implementing a 6th order FIR/IIR filter with latency <250 ps per update
4) full-instantaneous-bandwidth ADC and DAC (no sampling/decimation)

ideally, the net latency through the DSP core, ADC, and DAC would be <500 ps,
and preference is usually ARM cores, if that is an option.

if you cannot suggest a <1 ns latency solution,
what is the highest rate ADC+DAC+DSP you might recommend?

thanks 

t

  • Hi t

    I'm not sure if it is possible to meet those aggressive latency targets.

    I will discuss this with my colleagues and respond as soon as possible.

    Best regards,

    Jim B

  • Hi t

    The ADS5400 (1GSPS, 7ns latency) and DAC5670 (2.4 GSPS, 4.42 ns latency) are the lowest latency converters currently available.

    Please post your question to one of the DSP forums to find the lowest latency solution there. I think this forum is probably the one to try first: https://e2e.ti.com/support/dsp/c6000_multi-core_dsps

    Best regards,

    Jim B

  • Hi Thomas,

    After my investigation, I found it's impossible to implement the <1ns latency through the ADC->DSP->DAC link without any algorithm processing. Even <100ns is impossible also.
    Do you have any updates?

    Regards,
    Feng

  • So far, i have no better answers than the ones in this thread.  Most GHz-class converters seem to have pipelines for all vendors i have found so far.  I haven't really looked at the DSP latency yet, perhaps that is where you are drawing your 100 ns conclusion?  At least the ADC and DAC above seem to give some hope of 10 ns times, have you found >50 ns latencies in the DSP?  I presume the added latencies are somehow associated with the serial data transfer?  Let me know if you drew some conclusion on DSP core latency, and what DSP core you considered?

    So far, my overall experience is that the latency of GHz-class ADC+DAC in nanoseconds is very nearly the same latency as 100MHz-class systems.  So, I seem to end up with 10-20 clock ADC+DAC latency at GHz, and just a few clock cycles at 100 MHz.   A rather surprising roadblock to me. 

  • Hi Thomas,

    I am not sure about the latency caused by DSP.
    Actually, I want to implement the link like this ADC->FPGA-DAC.
    When I said the latency is impossible less than 100 ns, I mean that even if the latency caused by ADC and DAC is 10 ns, which seems like the lowest latency, the latency caused by ISerdes and OSerdes still is considerably large.

    The ISerdes( or OSerdes for DAC) is related the channel between ADC output and FPGA logic cells, which performs the algorithm.
    I mean the latency of high speed parallel data transfer between the input pin of FPGA and the internal logic cells is considerably large, maybe 100 ns as my estimation.

    The DSP's situation could be the same as FPGA above.
    Because we want to use very high sample rate ADC/DAC, we must choose the DSP including the JESD204B interface. Because I had not found one DSP which can support 14 bit parallel high speed data(>1Gsps) interface to ADC using parallel LVDS output.
    As I know the JESD204B has quite large latency because of its SerDes, typical value of its latency maybe 100 ns as I acquire from some ADC/DAC's datasheet.
    Two docs could be helpful here, www.ti.com/.../tidu171.pdf and www.ti.com/.../ads54j60.pdf.
    This is my thought about why I mentioned the value less than 100 ns could be impossible.

    As one word, because we want to use high speed ADC/DAC to interface the DSP, we must choose the DSP inlcuding the JESD204B interface, which latency of the SerDes could be very large, almost 100 ns.
    Also, if we want to interface the high speed ADC/DAC to FPGA, we can choose the ADC/DAC using paralell LVDS as its output/input to reduce the latency caused by ADC/DAC, however the ISerDes/OSerDes in FPGA also introduce large latency.

    From my undersatnding above, the latency of high sample rate(>1Gsps) link ADC->DSP/FPGA->DAC could not be less than 100 ns (maybe the lower limit could be larger ).

    And if anyone has one perfect solution to reduce the latency less than 10ns, please correct me immediately!!!

    Hope this could help you even a little. By the way, are you developing the automotive radar target simulator like me? I guess this from your latency requirement.

    Regards,
    Feng