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"unexpected SYSREF" error

Bart Noordsij91
Prodigy 40 points
Other Parts Discussed in Thread: LMK04828, DAC39J84

Hi,

I have a custom PCB with an LMK04828 and four DAC39J84 devices (LMFS 2441, 2x Interpolation) connected to the HPC1 of a VC707 or our CES820(with a KU040 FPGA)
transceiver rate=10.3125Gb/s, FPGA refclk=258.125MHz, DACCLK=516.25MHz, VCOclk(SERDES)=2581MHz
the SYSREF is a single pulse coming from the pulser (synchronous to the VCOclk/10), based on a SYNC pulse coming from the FPGA, synchronous to the TXOUTCLK coming from the transceiver (258.125MHz)

I can initialize all devices and get proper data from all channels on both carriers, however when I send another SYNC pulse, on the CES820 I read 0x1007 from register 0x6C, whereas on the VC707 it's 0x7, which is what I expect. When I change the VCOclk_divider to 160 (to synchronize the SYSREF pulse to the LMFC), both carriers work fine.

what might be the difference between the settings of the DAC and LMK to cause this difference?

Thanks,
Bart Noordsij

  • 0
    TI__Guru* 91947 points

    Bart,

    These are register reads from the CES820 which contains the FPGA correct? If so, they sounds like a question for Xilinx. Is the SYSREF input to the DAC boards AC or DC coupled? If it is AC coupled, a single pulse could easily cause problems.

    Regards,

    Jim

  • 0 in reply to jim s
    Prodigy 40 points
    Hi Jim,

    Thank you for your quick response, this is a register inside the DAC, the signal is DC coupled.

    Bart
  • 0 in reply to jim s
    TI__Guru* 91947 points

    Bart,

    I repeated this test with our TSW14J56EVM and read back a 0x0007 after I cleared this register. When I first read it, the value was 0x300F. Then I read the following from the  register map description:

    "Driven high if the PLL in the SerDes block0 goes out of lock. A false alarm 0 is generated at startup when the PLL is locking. User will have to reset this bit after start to monitor accurately".

    Could this possibly be the issue you are seeing? Did you do a read after clearing the register?

    Regards,

    Jim

  • 0 in reply to jim s
    Prodigy 40 points

    Hi Jim,

    The DAC is configured to only use link0, so SERDES PLL rw1 doesn't have to lock, the same applies to the DAC PLL.

    Attached you'll find the configurations of the DAC and LMK:

    • initialize LMK [80]
    • initialize DAC [573]
    • send pulse
    • read back DAC status [816]
    • send pulse
    • read back register 0x6C

    FMC216.cpp

    Bart

  • 0 in reply to Bart Noordsij91
    Prodigy 40 points
    Hi Jim,

    The has been resolved, I used an incorrect SYSREF divider inside the LMK.

    Bart