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DAC8812 Timing

Hong Tay
Expert 2465 points

Other Parts Discussed in Thread: DAC8812

Hi Sir,

Please help to clarify the understanding is correct.

When we transfer data through SPI with 3 bytes, it will take 24 bits.  And the way SPI in the MCU works, the Slave Select(SS) or Chip Select(CS) will return to logic high after sending the third byte, the 24th bit.  Based on the statement above and the timing diagram, we have to pull up the CS line after the 18th bit,  

 

If I have a data  0x010203. And I will send it to the DAC through SPI.  Since the MCU will pull up after the 24th bit after sending the 3rd byte, this will mean that the Serial Input Register will contain  00 0000 0100 0000 1000 in binary or 0x000408.  Is my understanding correct?

Hope to hear from you soon. Thanks.

  • 0
    TI__Mastermind 46290 points

    Hong,

    The diagram is only specifying a minimum time requirement between the last rising clock edge and the rising edge of chip select. The Timing Requirements table on page 6 defines TCSH = Clock to CS hold = 10ns minimum. This is consistent with the illustration in Figure 1. Keep in mind that this illustration is just an example of one method of communicating with the device used as a means to explain the Timing Requirements table contents.

    On page 15 and 16 the behavior of the SPI interface is described. Of particular interest is the last sentence in the first paragraph on page 16: "For the DAC8812, only the last 18 bits clocked into the serial register are interrogated when the CS pin returns to the logic high state". Therefore using 24-bit SPI frames with the appropriate timing and clock phase and polarity, the data content would be:

    <Bits 23:18 = Don't Care><Bits 17:16= Address><Bits 15:0 = Data>

    In other words, the data sent to the DAC should be aligned to the last 18-bits as opposed to the first 18-bits. I hope that makes sense.