adc12j4000 data corruption with Xilinx board

D,

Are you using the TSW14J10EVM with the other two boards as well? Which Xilinx board are you using?

Regards,

Jim

I used S-AXI interface to invert gtN_rxpolarity_in bit in register 0x604 of JESD204PHY interface. I am not seeing any improvements on data. Is there a particular sequence to be followed?

D

Short/Long Transport test

Jim,

Again, when I verify the data from ADC test samples with FPGA SERDES p/n swapped, the pattern seen is as :

Is it a case of data decode issue or data corruption issue? Four lanes are fine while other four are not.

Hi D

I'm not sure why half of the lanes would have issues and half would be OK.

Have you taken a look at the example Xilinx firmware provided in the TSW14J10EVM product folder?

Here is a direct link to that firmware source: http://www.ti.com/lit/zip/slac690

Best regards,

Jim B

Hi D

One other question. I know the KC-705 board only has 4 GTX transceivers connected to the HPC FMC connector.

Does this Digilent board have 8 (or more) GTX transceivers connected to the FMC connector that you are using?

Thanks,

Jim B

Jim,

I was finally able to get it working. All the data are correct now.

Digilent uses same FPGA as KC-705, which can support only up to 8 channels.

I think it will be better to have some warning signs on PCB itself when P/N on FMC changed on this board. Although, it is bad design practice for engineers  to overlook pin assignments, these are frequently missed things when evaluating multiple similar evaluation boards that conceptualize standard assignments.

Thanks for all your support.

D

Hi D

Sorry about the confusion caused by this slightly non-standard mapping.

I will add a warning to the ADC12J4000EVM User Guide to address the lane polarity issue.

Best regards,

Jim B