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ADS1118: Conversion Modes

Eric Sklarchuk
Prodigy 50 points
Other Parts Discussed in Thread: ADS1115

Hi ... I am just trying to understand the various conversion modes for this device.  I am designing an FPGA interface to this device, where the FPGA serves as the SPI Master.  I plan on using the device with 4 single ended analog inputs.  Each input should be sampled every 10ms.

Just want to confirm that for each SPI transaction the Config Register configures the channel for the next conversion, and the SPI data read back for this same SPI transaction  is from the previous configuration.

Single Shot Sequence

1. SPI #1: Configure for AIN0 ... read back dummy data.

2. SPI #2: Configure for AIN1 ... read back data from AIN0 conversion.

3. SPI #3: Configure for AIN2 ... read back data from AIN1 conversion.

4. SPI #4: Configure for AIN3 ... read back data from AIN2 conversion.

5. SPI #2: Configure for dummy (any) channel ... read back data from AIN3 conversion.

Is it possible to internally time the expected conversion time of each channel between SPI transactions without using DRDY_N?  I would really prefer not to use DRDY_N.

OR ... between the SPI transactions above, should CS_N be brought LO without SCLK to wait for DRDY_N to assert LO) before continuing with the next SPI transaction?

OR ... should the SPI transaction start (i.e. CS_N LO and SCLK toggles for toggles for 16 cycles) ... then stop SCLK and keep CS_N LOW until DRDY_N asserts to LO ... then negate CS_N?

 

 

Continuous Conversion

1. Not sure if this mode makes sense in my application.  I assume the ADC only continuously converts the single channel it has been configured with?

2. How would continuous conversion mode be used with all 4 channels sequentially?

  • 0
    TI__Intellectual 1610 points
    Hello Eric,

    Thank you for your query.

    You are on the right track by using the single-shot mode and following the single shot sequence you provided above. I would avoid continuous conversion mode in this situation.

    If each input need to be sampled every 10 ms, I would recommend to use the 128 SPS data rate for maximum throughput and performance.

    At 128 SPS, the ideal conversion time will be 7.8125 ms. Accommodating for the +/-10% internal oscillator variation, the conversion time will be ~8.6 ms. We need to add another ~0.1 ms for the device to power-up and start the conversion in single-shot mode. Hence, the worst case time required to read the new conversion data after switching to another channel is 8.61 ms. In other words, as long as you have greater than 8.61 ms delay before you read the data after changing the register setting to move to another channel, you should be good. Please note that this worst case conversion time excludes the inaccuracy of the timing of the FPGA. However, if the FPGA SPI timing can be controlled within the remaining 1.39 ms (which most FPGAs should be capable of), one can execute the above provided single shot sequence every 10 ms without polling on the DOUT/DRDYn pin.

    Let me know if you have more questions.

    Thanks,
    Krunal
  • 0 in reply to Krunal Maniar
    Prodigy 50 points
    That answers my configuration questions.

    One more question regarding the 0.1ms power-up time mentioned in your response. Where is this time mentioned in the datasheet? I cannot seem to find it. Other threads have mentioned a 20us power up time.

    Does this mean I have to bring CS_N low for the startup time, prior to starting SCLK? However, this would go against the tCSSC timing spec of 100ns.
  • 0 in reply to Eric Sklarchuk
    TI__Intellectual 1610 points

    Eric,

    You are correct, there is about 20 us start up time for the device to wake up and start a conversion in single-shot mode. Since, you seem to have some margin in your design, I approximated the power up time to a bit on the high side. We will add this information in the next datasheet revision for better clarity.

    No, the device responds to commands in single-shot mode and is not related to this startup time. Only the SPI timing requirements need to be met to communicate with the device.

    Thanks,
    Krunal

  • 0 in reply to Krunal Maniar
    Prodigy 40 points
    Hi,

    Somebody can answer Eric's questions in the original post, regarding the multiple channels in "continuous conversion" mode?

    I have the same questions for the ADS1115 device (with I2C interface).

    Thanks,
    Denis