ADC08DL502 DCLK to Out of Range output delay

In our design we use the ADC08DL502 ADC. I am trying to read the ADC output data into an FPGA. To be able to read the Out of Range output, I would like information about the "Input Clock to Out of Range output delay" or even better the "DCLK to Out of Range output delay". I cannot find any information about this in the data sheet. Is there any detailed information about the timing of this Out of Range signal?