• State
  • Locked Locked
  • Replies 2 replies
  • Subscribers 46 subscribers
  • Views 535 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DAC3151 - Timing requirements

Sunset
Genius 13625 points

Hello Team,

I'm trying to better understand the timing requirements shown on paragraph 6.8 related to the LVDS INPUT TIMING of the datasheet.

In particular Figure 1 shows that the bit is made of ts(DATA) and th(DATA).

From the table, taking the first two lines of each timing, I have:

Ts


and

Th

in the timing plot below it looks like that if Ts increases, Th should decrease. From the table this is not true.

From that perspective, I'm probably misinterpreting something. May I ask you to rephrase I could interpret the table values?

Thanks,

SunSet

  • 0
    TI__Mastermind 29220 points

    Hi,

    notice in the two line entries that you copied that with no delay setting the default data valid window is to the right of the clock edge, with *negative* setup time.   That means that the data valid window starts 20ps after the clock edge and extends to 310ps after the clock edge.    Adding one step of delay to the clock shifts the data valid window more to the right, with setup time now -120ps and hold time 390ps.   That is, since the clock is now delayed a bit, the valid data window is also 'delayed' or shifted to the right.  But the overall size of the data valid window doesn't change much, being fairly constant.   290ps wide in the first case and 270ps wide with one step of clock delay added. 

    Regards,

    Richard P.

  • 0 in reply to Richard Prentice
    TI__Genius 13625 points

    Thanks,

    SunSet