Hello,
I am trying to interface an ADS54J60 EVM card from TI to a VC707 Virtex 7 eval card from Xilinx.
Both the Xilinx JESD receiver setups and the TI ADC setups need to be correct. I think I have the LMK04828 setups correct. Also, I have a lot of
help from Xilinx to get their JESD IP setup correct. So that leaves TI.
Below is the file (ADS54J60_LMF_4211.cfg) that TI provides to config the ADC for LMK=4211 mode, no decimation.
My question is, are you sure this will do all the required ADC configs? Why do ADS54J60 data sheet, tables 16,17,18 look so different?
Thanks, John Reyland
LMK04828
0x10F 0x66 //Enable SYSREF to ADC
ADS54Jxx_ANALOG
0x0000 0x81 // software reset
0x0011 0x80 // select master analog bank select page
0x0059 0x20 // always write 1 to bit 5
ADS54Jxx_DIGITAL
0x6800f7 0x01 // digital reset
0x680000 0x01 // reset digital
0x680000 0x00 // clear reset
0x6A0016 0x02 // JESD PLL MODE 40x
0x690001 0x04 // JESD Mode (bits 2-0), JESD Filter (bit 5-3)
0x690000 0x80 //set CTRL K in register 6
0x690006 0x13 //set K to 20
LMK04828
0x10F 0x06 //Disable SYSREF to ADC