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ADS54J60 interface

John Reyland62
Intellectual 375 points
Other Parts Discussed in Thread: ADS54J60

Hi Jim,

 
Thanks for your prompt reply.   
 
When my Xilinx JESD204 lowers the _SYNC output to the ADS54J60 then the ADC outputs  about 5000 lines of '00ff00ff18af817100ff00ff866d81cc' to the JESD.  I picked this up from the Xilinx ILA (Integrated Logic Analyser) . 
 
ADC output '00ff00ff18af817100ff00ff866d81cc' has 128 bits that should match the LMF4211 diagram on page 35 of the ADS54J60 data sheet.  There is a better description of these bit in Xilinx document PG066, page 53. 
 
Finally the JESD raises the _SYNC output to the ADS54J60 and the data changes, but it still does not make sense.
 
Are there any changes to the setup file I sent you that might be needed to fix this?
 
Below are my basic ADC parameters.
 
Thanks,
John Reyland
 
 
JESD Parameters for ADC ADS54J60 to FMC2 to Virtex 7, LMFS = 4211
L = 4 = number of lanes
M = 2 = number of ADCs transmitting over JESD link
F = 1 = number of octets/(frame and per lane)
S = 1 = number of samples/frame (i.e. each ADC sends 1 samples in each frame)
K = 20 = frames/multiframe
ADC sample clock = 491.52 MHz
Each ADC output occupies 2 lanes 
Frame clock = core_clock = frequency set to deliver 32 bits/lane on JESD output 
Frame clock = 491.52/4 = 122.88 MHz   
JESD line rate = 40*(frame clock) = 4915.4 MHz 
SysRef frequency = (Line rate)/(10*K*4) = 4915.4/(10*20*4) = 6.144 MHz
LMFC rate = 24.5770 MHz 
See ADS54J60 data sheet, page 35
 
 
 
 
  • 0
    TI__Guru* 91947 points

    John,

    It appears you are not establishing CGS. You should be getting BCBCBCBC... from the ADC on every lane when SYNC is low and CGS is working. The firmware Xilinx created for us used both a Core clock and Reference clock. Are you using two clocks with your design? If you looked into using the TI TSW14J10EVM and TI HSDC Pro GUI to help you get started with this interface?

    Regards,

    Jim 

  • 0 in reply to jim s
    Intellectual 375 points

    Hi Jim,

    Thanks for the info about CGS data BCBCBCBC.  

    Yes, I believe I have the Xilinx JESD204 IP setup properly.  The Xilinx FAE for Rockwell Collins checked my project coding over carefully.

    VC707 Virtex 7 EVM I am using has 2 high pin density FMC.  First FMC drives a TI DAC 37J84 EVM.  The DAC interface works perfectly, I really like that DAC.  

    The ADS54J60 EVM is connected to the second FMC,   There is one thing we might have wrong.   The ADC outputs DA1, DA2, DB1, DB2 are connected as shown below from my constraints file.   rADCx[0:3] is the 4 lane JESD input to the Xilinx JESD PHY IP.    Do you think this is right please?  

    Thanks,  John Reyland

    # DA1 - FMC2_HPC_DP4_M2C (FMC2 pins A14,A15)
    set_property PACKAGE_PIN W5 [get_ports {rADCxn[0]}]
    set_property PACKAGE_PIN W6 [get_ports {rADCxp[0]}]


    # DA2 - FMC2_HPC_DP6_M2C (FMC2 pins B16,B17)
    set_property PACKAGE_PIN U5 [get_ports {rADCxn[1]}]
    set_property PACKAGE_PIN U6 [get_ports {rADCxp[1]}]


    # DB1 - FMC2_HPC_DP0 _M2C (FMC2 pins C6,C7)
    set_property PACKAGE_PIN P7 [get_ports {rADCxn[2]}]
    set_property PACKAGE_PIN P8 [get_ports {rADCxp[2]}]


    # DB2 - FMC2_HPC_DP2_M2C (FMC2 pins A6,A7)
    set_property PACKAGE_PIN L5 [get_ports {rADCxn[3]}]
    set_property PACKAGE_PIN L6 [get_ports {rADCxp[3]}]