Regarding ADC12J4000 configuration

Hi Jim,

Thank you for your  response. We are not using Evaluation Module, it's our own designed board.

Regards,

Yogita

Hi Jim,

Attached are the log files for ADC data for actual and pattern mode.Test Pattern Data.xlsActual_Data.xls

Hello Jim,

May I know if any updates are there?

Regards,

Yogita Nirmale

Yogita,

Jim is on vacation this week.  He will respond once he returns.

Ken

Hi Yogita

The ADC12J4000 device intentionally inserts "Alignment characters" into the data stream in accordance with the JESD204B standard. The characters sent are K28.7 (FC) and K28.3 (7C). 

The receiving IP must follow the same rules to detect the monitoring characters and follow the standard requirements. If the characters are showing up in the expected locations the replacement rules are followed to re-insert the proper data value. If the characters are in unexpected locations then the receiver will proceed with re-alignment.

Please see this earlier post describing this: https://e2e.ti.com/support/data_converters/high_speed_data_converters/f/68/p/497381/1799275#1799275

There is example Xilinx JESD204B capture firmware available in the TSW14J10EVM folder. The direct link to the firmware source is here http://www.ti.com/lit/zip/slac690

This firmware is applicable for the Xilinx KC705, ZC706, VC707 and KCU105 platforms. Please review that to understand how the alignment character processing is handled.

Best regards,

Jim B

Hi Yogita

Please let us know if you were able to resolve the issues you were seeing.

Best regards,

Jim B

Hi Jim,

We realigned the JESD lane data as per our discussion. And the ADC 12 bit signed data received for noise level (no ADC input) was as per the attached file. May I know the reason for only two repeating values?

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Regards,

Yogita Nirmale

Hi Yogita

That is not the data I expect to see when no signal is applied. The value should be around 0111 1111 1111 and 1000 0000 0000 0000 transition point with some noise in the least significant bits.

Can you enable the ADC Test Pattern mode and capture data again? Comparing that data to the expected pattern may help you understand what is wrong.

When the data from the frames is ordered properly the sequence received should be as follows, repeating every 80 samples (2 frames).

Best regards,

Jim B

Hi Jim,

We are getting the pattern which you have mentioned in previous mail, but not directly, upon some rearrangement of bits we are getting it. So we have done same rearrangement for actual data as well. Here I am attaching both pattern test log(first file) and actual data without ADC input log(second file). Kindly go through it and help us through it. In the attached files, the gtx_data are 33 bits, where the 33rd bit is 'k_char; signal while lsb 32 bits are the received lane data. The data is taken on releasing the Sync signal(which is also included in log file).

Regards,

Yogita