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Two TSW54J60 EVM with one TSW14J56 EVM

Tobias Witte
Prodigy 130 points

Hello Team,

I bought two TSW54J60 Evaluation Modules (Link: www.ti.com/.../tsw54j60evm) and one TSW14J56EVM Evaluation Module (Link: www.ti.com/.../tsw14j56evm). The aim is to read four high speed signals with the two TSW54J60 Evaluation Modules and analyse them with one TSW14J56EVM. I want to design an extra PCB in Y-shape which has two FMC connectors for the  TSW54J60 Evaluation Modules and one FMC connector for the TSW14J56EVM Evaluation Module. Each ADC will use two lane mode of the JESD204 interface for sending data. I want to store all data in the DDR and finding the maximum of each ADC values. For my implementation I need to do several modifications in the verilog code (ring buffer, timestamp, triger for sending data to PC,...). I started to analyse the RTL schematic of the TSW14J56REVD_V3.03_FPGA_FIRMWARE (Link: www.ti.com/.../tsw14j56evm) last week. As I understand correctly the datahandling between the ADC inputs and the DDR3 is done by the CYUSB301X controller. This leads me to the verilog modules fx3_main and fx3ctrl. Because of the huge size of the RTL schematic, the amount of modules and the low amount of comments in the code its difficult to understand the datapath and where to do my modifications. Maybe you can help me and answer my questions:

1. Can you give me more informations to the code?


2. The data handling between PC and TSW14J56REVD is done by the CYUSB301X. If I understand correctly I need to modify the C-code of the ARM926EJ on the CYUSB301X. Is it possible to get the code and transfer a modified version to the ARM-controller?


3. Which pins on the FMC connector of the TSW54J60 will be used for sending data If I use both ADC´s in two lane mode? Will it be DB0P, DB0M, DB1P, DB1M in case of channel B?

Best regards

Tobias W.

  • 0
    TI__Guru* 91947 points

    Tobias,

    I have forward this to the firmware/software development team. I hope to have some info for you in the near future.

    Regards,

    Jim 

  • 0 in reply to jim s
    TI__Guru* 91947 points

    Tobias,

    For #1,

    We don’t have a detailed documentation for the FW except a high level design documentation which is attached. This document will explain different IPs used in the FW from the design standpoint.

     

    For #2,

    As long as the interface between FPGA and Cypress FX3 is kept same (in this case I don’t see a need to change), the FX3 FW can remain unchanged. But we don’t have any documentation at this point of time except the source project. Is this something you could use?

    For #3,

    The ADC will send data on DA1 (FMC pins A14/A15), DA2 (B16/B17), DB1 (C6/C7) and DB2 (A6/A7).

    Regards,

    Jim

    TSW14J56 RevD MC firmware design document.doc

     

  • 0 in reply to jim s
    Prodigy 130 points

    Dear Jim,


    thank you for the information´s and the document. I have three more questions and maybe you can help me:

    1. The two TSW54J60 board´s will use two lane mode for each ADC. The Y-PCB will connect  DA1, DA2, DB1 and DB2 from one TSW54J60 to RX0 - RX3 on the TSW14J56 board and DA1, DA2, DB1 and DB2 from the other TSW54J60 to RX4 - RX7 on the TSW14J56 board. So I use all hsma_rx_p lanes to the JESD204B IP core. If I use this setup how will the data get to the PC if I use the MATLAB dll for example?  Will this work or are there some modifications in the verilog to do for store the date in the DDR correctly and send them to the PC?

    2. I need to synchronyze the two TSW54J60 boards. Is there a possibility to get both CLK´s as inputs of the FPGA and synchronize them in Software or do I have tu use the external ADC Clock input of the TSW54J60 boards with an extra clock?

    3. Can you send me some more information about both boards to understand more about the structure and implementation of them?


    Best regards

    Tobias W.