Other Parts Discussed in Thread: ADC12D1600RF, ADC12D1600, ADC12D800RF, ADC12D500RF, ADC12D1600RB, WAVEVISION5, ADC10D1000
Hello,
I'm currently evaluating the ADC12D1600RF ADC in nonDES Mode using the ADC12D1600RFRB Evaluation Board and the WaveVision 5 Software. One of the performance parameters I'm evaluating is the chip's performance at a variety of sampling clock frequencies. I successfully reconfigured the Evaluation Board to use the external clock connection and I am able to collect samples at sampling clock frequencies of 420 MHz and higher.
However, I am NOT able to collect samples with sample clock frequencies lower than that. For example, when I set the external sampling clock frequency to 400 MHz, the WaveVision 5 software displays an error saying the board is unable to detect the sampling clock and the "DCLK_LOCKED" LED on the Evaluation Board is OFF. If I increase the frequency to 420 MHz, the "DCLK_LOCKED" LED turns on and I am able to collect samples again. I also tried setting the Low-Frequency Select (LFS) register bit high to see if that helped but it didnt appear to make a difference.
The ADC12D1600RF data sheet says the ADC chip supports a Minimum Sampling Clock Frequency of 300 MHz (150 MHz with LFS set high) in nonDES mode so I *should* be able to use a sampling clock rate of 400 MHz. I checked the datasheet on the balun in the Sampling Clock path and its rated down to 400 MHz so it should be fine. Is there something else in the hardware design of the the ADC12D1600RFRB Eval Board that prevents reaching Sampling Clock rates of 400 MHz or lower? Or is there a problem with the Evaluation Software?
Thanks,
Bob
