• State TI Thinks Resolved
  • Locked Locked
  • Replies 1 reply
  • Answers 1 answer
  • Subscribers 46 subscribers
  • Views 418 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Minimum clock pulse width requirement of ADC128S102QML-SP

Kenneth Pham
Prodigy 80 points
Other Parts Discussed in Thread: ADC128S102QML-SP

Greetings,

I wonder if there is a minimum pulse width requirement on the clock provided for ADC128S102QML-SP to ensure its correct functional operation. In our current implementation using an FPGA to interface with ADC128S102QML-SP, during the assertion of CS/ there is a glitch of a few nanoseconds generated at the end of 64 clocks generated for the ADC128S102QML-SP SCLK. Will this narrow glitch cause the ADC128S102QML-SP internal control logic to become deadlocked and fail to properly function in the subsequent conversion?

Thank you.

  • 0
    TI__Genius 16890 points

    Hello Kenneth,

    The minimum spec for a clock pulse is 3.125ns (1/16MHz )/2.  The part will probably recognize a pulse shorter than that as a clock pulse.  

    If I understand your problem right, you bring CS low, you have 64 clock pulses (4 ADC readings) and then you bring CS high.  As CS is going high there are some glitches on the clock line.  If the glitches are not too fast the ADC will recognize them as a start of a new reading, but once CS is high everything is reset.  When CS is brought low again it starts a new reading.

    Mike