ADC12J4000 HDL simulation model

Fosfor

Prodigy 35 points

Other Parts Discussed in Thread: ADC12J4000

Dear community,

is there any (S)Verilog/VHDL simulation model of the JESD240B interface part of the ADC12J4000 converter available?

Thank you for any advice,
Fosfor

over 8 years ago

0 Jim Brinkhurst1 over 8 years ago

TI__Mastermind 44680 points

Hi Fosfor

There is no Verilog/VHDL model available. The ADC12J4000 product folder has links to an IBIS-AMI model to allow signal integrity modeling.

Our evaluation tools provide links to source code for Altera and Xilinx example capture firmware.

The Altera firmware is available in the Software section of the TSW14J56EVM product folder here (click on the Show More link to show all software items):

http://www.ti.com/tool/tsw14j56evm#Technical%20Documents

The Xilinx firmware is available in the TSW14J10EVM product folder here:

http://www.ti.com/tool/tsw14j10evm#Technical%20Documents

Best regards,

Jim B

0 Fosfor over 8 years ago in reply to Jim Brinkhurst1

Prodigy 35 points

Hi Jim,
thank you very much for a quick response. I already have the Altera example design as a reference for our project. I'll do a quick search for some general JESD204B verification core and if I do not find any I'll make some simple model. So far, I just need "something" to verify the concept and interconnection of all the components before testing it on HW.
With all the best,
Fosfor

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ADC12J4000 HDL simulation model