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Recommended clock distribution device

Izik
Expert 1585 points
Other Parts Discussed in Thread: DAC3482, DAC38J84, LMK04828, ADC3423

Hello 

I need help with selecting a clock distribution device to support the following signals: 

My input is 1920MHz (could be also 960MHz if needed)

I need to generate the following clocks:

 

FPGA: 80MHz LVDS or LVPECL

3XADC34J23 sampling clock 80MHz

3XADC34J23: Sysref What frequency do you recommend?

Timing IO: 80MHz LVDS or LVPECL

DAC3482 Sysref - What frequency do you recommend?

DAC38J84 Sysref - What frequency do you recommend?

 

No need for PLL/jitter cleaner - my signal is very clean

Low power and small size is critical - if it's better to use two parts please advise

 

Very important: The clock to the FPGA must be active without any digital settings sent to the device, since there is no FPGA without the clock (the chicken or the egg issue)

Many thanks

  • 0
    TI__Mastermind 44680 points

    Hi Izik

    I think it may be difficult to achieve everything you need with a single device.

    I would recommend using a standalone oscillator for the FPGA housekeeping clock to allow that device to start up OK.

    Then you can use the LMK04828 in distribution mode to create the necessary Clock and SYSREF signals for the ADCs, DACs and FPGA. It has all of the features you need for that purpose.

    The proper SYSREF frequency depends on the data formats and K values set in the ADC and DAC devices.Can you provide the LMFS settings you plan to use for each device?

    I see the ADC sampling clock will be 80 MHz. And I think your DAC data clock is also planned to be 80 MHz, is that correct?

    Once we have all of that information we should be able to determine the best K values and the SYSREF frequency.

    Best regards,

    Jim B

  • 0 in reply to Jim Brinkhurst1
    Expert 1585 points
    Hi

    I made a typo on the previous message, I'm using ADC3423 (not the JESD204B)

    The config for DAC38J84 is LMF=244
    The DACCLK for DAC38J84 is 1920MHz, DACCLKC for DAC3482 is 960MHz
    The data rate from FPGA is 240MSPS to both devices.
    DATACLK to DAC3482 is 480MHz

    The DACs and the ADCs don't have to be synchronized

    Do I need to send SYSREF also to the FPGA?

    Thanks
    Izik
  • 0 in reply to Izik
    TI__Mastermind 44680 points

    Hi Izik

    The LMK04828 can create the following clocks that you'll need based on the 1920 MHz source clock that you have.

    1) ADC3423 x 3 - 3 clocks at 80 MHz (1920 / 24)  (You might need to use a simple 1:4 clock fanout device to clock all 3 ADCs if the total number of high frequency clocks is more than 7)

    2) DAC38J84 - DACCLK at 480 MHz (1920 / 4) use internal multiplying PLL to create 1920 MHz, a slower DACCLK makes it easier to meet setup and hold times with SYSREF if needed.

    3) DAC3482 - DACCLK at 480 MHz (1920 / 4) use internal multiplying PLL to create 960 MHz.

    4) DAC3482 - DataCLK at 120 MHz (1920 / 16)  (DataCLK is half the rate of the data since both edges of clock are used).

    6) FPGA - 120 MHz (This is F_lane / 16 which is in the typical range for an FPGA. Check with your FPGA requirements to confirm, clocks at any divide factor of 1920 MHz can be created)

    7) SYSREF for FPGA and DAC - Assuming interface LMFS = 2441, and K is set to 2 then F_LMFC = F_lane / (10bits/oct * 4 octets/frame * 2 frames/multiframe) = 30 MHz. SYSREF can be at any frequency where F_SYSREF = F_LMFC/n where n is a positive integer.

    Calculation of F_lane needed to determine F_LMFC:

    F_DATA = 240MSPS * 16bits/sample * 10bits/8bits = 4.8 Gbit/sec total

    F_Lane = 4.8 Gbit/sec / 2 lanes = 2.4 Gbit/sec / lane

    I believe the FPGA JESD204B IP will require a continuously running SYSREF to function properly. The DAC38J84 also requires SYSREF for proper operation.

    If you have specific questions about any of these ADC or DAC devices, or the LMK04828, please post a new question in either the High Speed Data Converter forum, or the Clock and Timing forum.

    Best regards,

    Jim B