When using the ADS42JB69 in JESD204B subclass 2, what should be done with the SYSREF pins?

I'm working on a design where I am using one TI ADC ADS42JB69 and one DAC DAC37J84. The design will operate below 200 Msps and use subclass 2, which uses just the SYNC~ signal for deterministic timing.  What is the appropriate handling of the unused SYSREF pins?  The DAC37J84 datasheet explicitly states they can be left open, but have not found direction for the ADS42JB69.  Thanks.