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ADC12D1600 Questions on Bonding/ Skew

Richard Elmquist
Mastermind 45250 points
Other Parts Discussed in Thread: ADC12D1600

I have a customer asking the following questions:

I have a question in regards to ADC channel requirements. Does it require bonded mode interface?

I would like to know if the TI ADC will require a certain amount of lane to lane data skew. I really need skew to be consistent between power up or resets also.

My question regards to RX channel-to-channel skew tolerance of the TI ADC.  Just an example, I have used ADC12D1600, but I would like to provide channel bonding guidelines on FPGA TX channels.  Our JESD204B IP allows users to select bonded or non-bonded option.  When bonded mode is selected, skew among the FPGA TX output signals (I, Q and clk) are constant after reset / power up cycles.  When non-bonded mode is selected, there won’t be a constant skew relationship between the TX channels.  By looking at block diagram of ADC12D1600, I cannot find see any de-skew block.  I was looking at ADC12D1600 data sheet 6.15 Timing Requirements section earlier, and found Figure 4. Clocking in Non-Demux Mode DES Mode showing the info, somewhat similar info I was looking for.  However, this diagram is based on assuming there is no skew between DI and DQ signals.

I was not sure how to answer these questions so I decided to see if you understood what the customer was talking about.

Thanks for your help with this!

Richard Elmquist

  • 0
    TI__Mastermind 44680 points

    Hi Richard

    I'm not sure why the customer is referring to JESD204B IP, since the ADC12D1600 has a parallel LVDS data interface. Data would normally be received into an FPGA using the high speed LVDS input pins, not the high speed serial transceivers associated with JESD204B.

    The tOSK parameter in Table 6.13 quantifies the skew between the DCLK and all DATA output pairs. Also, as noted in the Pin Functions table, DCLKI and DCLKQ are always in phase with each other.

    Figures 1, 2, 3 and 4 illustrate tOSK.

    Finally, the Test Pattern Mode (see Section 7.3.2.5) can be used to confirm proper alignment of received data from the Qd, Id, Q and I data ports as well as the ORQ and ORI over-range bits.

    I hope this is helpful.

    Best regards,

    Jim B

  • 0 in reply to Jim Brinkhurst1
    TI__Mastermind 45250 points

    Jim,

    I think that he is using JESD204B as an example where they allowed their customer's an option of whether to use bonded or a non-bonded option. I am not familiar with what he means by a "bonded" option. This is one reason that I sent this to you. I could not find any information on this on the web, but I thought that you would be familiar with what the customer is talking about.

    I am sending him your response. I will ask for a little more detail on this "bonded" option and I will post his response as soon as I receive it

    Thanks for your help with this!

    Richard Elmquist