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DAC38J82 output SFDR and Harmonics does not meet at particular decimal frequencies

balaji yoki
Prodigy 70 points
Other Parts Discussed in Thread: DAC38J82

We are using DAC38j82 to perform waveform generation in the band of 20 - 500 MHz and sampling at 1.2 GHz.Required SFDR and harmonic suppresion for our application is 60 dBc.During initial testing in the above mentioned band we are able achieve the specfications , until outputs were generated in following manner

  • For 200.354 MHz - SFDR and harmonic suppression > 60 dB.
  • For 200.001 MHz - suppression is below 50 dB.

four parallel DDS sampling at 300 MHz is implemented to meet the sampling rate of 1.2 GSPS.


Kindly provide insights on these whether issue location is at DDS or at DAC.

Also these spurious levels are only high at specfic points such as 40.001 MHz,80.001MHz,120.001MHz,160.001MHz,200.001 MHz,240.001MHz,280.001 MHz......440.001MHz & 480.001 MHz.

Below is the output spectrum at 240.001 MHz

Below is the spectrum for the 200.001 MHz.

  • 0
    TI__Genius 12965 points

    Balaji,

    The DAC performance is not dependent on decimal frequencies of the IF signal.  Is your DDS pattern coherent and is the length a multiple of 256 samples?  These are the requirements for a clean specturm.

    Performing an FFT of the DDS buffer (with no window) will also show you what you should expect at the DAC output.

    Ken.

  • 0 in reply to Ken C
    Prodigy 70 points
    Thanks Ken,

    We will perform the FFT and be back with results.
  • 0 in reply to balaji yoki
    Prodigy 75 points
    Hi Ken,

    We have performed the FFT 4.5KHz resolution at the output of the DDS buffer and it's fine for all the frequencies. Required SFDR specification for the DAC output is 60dB. We are using single channel output of the DAC & operating the DAC at 1.2GHz sampling rate with 4Lane configuration between FPGA & DAC. With 1.2GHz sampling rate, what is the maximum SFDR can we achieve?

    There is no sampling rate issue between FPGA & DAC. Because we are meeting 10Hz resolution throughout the band (0 to 600MHz).

    Below is the DDS output spectrum for 200.001MHz.

    Note : The data not taken in simulation mode. The data captured at run time with chipscope tool.
  • 0 in reply to Ken C
    Prodigy 75 points
    Hi Ken,

    We have performed the FFT at 4.5KHz resolution at the output of DDS buffer and it's fine for the all the frequencies. The required SFDR spec is >= 60dB for 20MHz to 500MHz. We are using single channel output of the DAC & operating the DAC at 1.2GHz sampling rate with 4Lane configuration between FPGA & DAC.

    With this configuration, what is maximum SFDR can we achieve?

    There is no sampling rate issue between FPGA & DAC. Because we are meeting the 10Hz resolution throughout the band.

    Below is the spectrum output at the DDS buffer. Note, The data not taken in simulation. It's taken inrun time with chipscope tool.
  • 0 in reply to Loganathan Natarajan
    TI__Genius 12965 points
    Hi

    I don't see any attached pictures. Can you send me a good buffer and a bad buffer file? I can try to replicate this on my setup. Can you send me details of your DAC configuration?
    Fdac=1.2Gsps
    Fdata rate?


    The typical SFDR specs are reported in the data sheet for the different modes and sampling rates.

    Ken.
  • 0 in reply to Ken C
    Prodigy 70 points

    Hi ken,

    Above attached a file for our full DAC configuration.

    Balaji,

    Datapatterns,

    India.

    DAC38J82 Configuartion.xls

  • 0 in reply to balaji yoki
    Prodigy 75 points

    Hi Ken,

    Here with I have attached the DDS_Buffer_data.rar file, which contains DDS buffer data for the frequencies 200MHz, 200.01MHz & 200.001MHz. Also I have attached the image files for the same frequencies taken from spectrum analyzer and DDS buffer data spectrum plot done in MATLAB. In MATLAB I have taken blackmanharris window for all the frequencies and its bin resolution is 4.577KHz.

    Thanks & Regards


    Loganathan NDDS_Buffer_data.rar

  • 0 in reply to Loganathan Natarajan
    TI__Genius 12965 points

    Hi Loganathan,

    I had a look at your files and there is problem with them.  They are not coherent.  The stop and start time points do not line up.  This jump at the start and stop points will create some energy which will look like spurs on the spectrum analyzer depending on your sweep time.  When you do an FFT in matlab, do not use a window function as this will make the spectrum look cleaner as it artificially forces the start and stop points to be continuous at the expense of widening the tone BW to several bins.  When the DAC generates the signal in the analog domain it will not have the ability to apply the window - it will recreate exactly what is in the buffer.  See below where I plotted the start and end points - you will notice a jump in the middle of all 3 plots (i plotted 10 points at the end followed by 10 points at the beginning)

    If you want them to be coherent or at least not have this jump, you can create tones that fall exactly in the middle of your bin.  The frequency will be an integer multiple of your bin size (N*Fdata/numsamples).  This does not allow you to have exact .01M or .001MHz resolution.  If you need .01M or .001M then you can apply a window to the signal before sending it to the DAC - the trade off here is that the tones will be shaped spectrally by the window, and you will lose some signal power based on the window shape (typically around 1/2).

    The reason your spectrum analyzer plots may look "clean" is that the spectrum analyzer may be just analyzing part of your buffer being played out of the DAC (its 5M samples long) depending on sweep time etc.  If you make your sweep time longer (increase number of samples analyzed) the spectral leakage/non-coherent  behaviour wil be more apparent.

    Ken.

    Ken.

  • 0 in reply to Ken C
    Prodigy 75 points

    Hi Ken,

    The given buffer is not my whole data. I just gave you only some continuous samples which is taken at run time. We are using Xilinx DDS Core for generating the frequency. It's coherent only. The DDS Core will role off automatically with continuous phase.

    Thanks & Regards'

    Loganathan N

  • 0 in reply to Loganathan Natarajan
    TI__Genius 12965 points
    Hi Loganathan,

    If that is the case and the output from the DDS is continuous and not buffer limited, then it may not be glitch energy related. Have you tried backing off the digital signal by a small amount, maybe 0.99x? If you are running fullscale there is a chance that the samples at certain frequencies could look repetitive cycle to cycle and result in unexpected harmonics.

    Typically having a signal at 200M, 200.01M and 200.001M should not be a problem from the DAC side.

    Ken