ADS4149EVM+TSW1400: "Clock from ADC EVM not received by FPGA board"

Pragyan,

If you are using parallel programing mode, make sure the jumpers are installed per table 1. The clock amplitude should be at least 5dBm. How much current is the 3.3V supply drawing after the clock is applied? It should be around 0.126A. What device are you selecting in HSDC Pro? Are you entering 150MHz in the ADC Output Data rate window?

Regards,

Jim

Hi Jim,

Thanks for your reply.

The 3.3V supply is drawing 0.53A, i'm not sure why? I selected ADS4149 in HSDC Pro and yes I entered 150MHz in ADC output data rate.

Thanks,
Pragyan

Pragyan,

What is the current limit on your power supply? Setup your board for parallel SPI mode and see what the current is at after power up. If it is still low, increase the amplitude of the input clock signal so that the amplitude at the device is 1.6V p-p. If it is still low, check all of the power jumpers to make sure you are getting the correct voltages to the IC power input pins.

Regards,

Jim 

Hi Jim,

Thank you again for your reply.

The current limit on my 3.3 V supply is 2.5 A and I have setup the board for parallel programming.  Could you tell me how to check the clock signal amplitude at the device? Is there another way than measuring at the IC pins? (I'm not sure if this is useful but the VCM is 0.95 V as per the datasheet) 

Thanks,

Pragyan

Hi,

while Jim is out of office for a few days I will try to help.   If the clock is not being seen by the TSW1400, as indicated by the LED D3 (I think that is the one) being off and by HSDCPro timing out when trying to capture, then that usually means that 1) the sample clock to the EVM isn't getting to the ADC or 2) there is an issue with power supply or 3) the data converter is not set up in the right mode of operation.  

If the jumpers on the EVM are set to match the User Guide for the default mode of operation for clocking and power supply, and the data converter is set for LVDS output, then the clock should be getting through to the TSW1400.   Check the picture of the EVM on the TI web page for the EVM  http://www.ti.com/tool/ADS4149EVM?keyMatch=ads4149&tisearch=Search-EN-Everything

There is a photo of the EVM that shows default jumper positions.  (The photo may be of revision A of the EVM and I think you may have revision B, but it is a start.   The EVM would not have changed much)  In that picture on the left you can see a jumper set for BIN, LVDS meaning offset binary output format, LVDS signaling.   If the data converter were set for single ended CMOS output signaling then the TSW1400 would not be able to sense the clock.  In that same picture, you can see a jumper for Parallel configuration of the device, not serial.  That means that the mode of operation is set by the jumpers on the EVM, not through the use of the SPI GUI to program the SPI registers.    On the right side of the photo are the default jumper positions for the power supply options.

If the mode of operation of the data converter is correct, then I would check supply voltages with a volt meter.  check that you are seeing 3.3V at the banana jack, and that you are seeing 1.8V at the jumpers that are labeled for 1.8V.  You may need to slide the jumper up just a bit to be able to touch the post, or use a jumper that is open top to be able to touch the post.

If the voltages are correct, then as Jim suggested check for clock.   Probe for sufficient amplitude of clock at the inputs to the data converter.  In that same EVM picture you can see that the clock routes to transformer T4 and after the transformer are two AC coupling caps in series (C65 and C66 it looks like.)  These caps are a convenient place to probe for clock amplitude.   A volt peak to peak differential would be nice (half that on each side of the differential signal if you just have a single ended probe to probe at one cap at a time) but if you are down below a few hundred mV then there may not be sufficient clock amplitude. 

If you do see a good clock at the sample clock input to the data converter, then you can probe for the LVDS clock out of the device to the TSW1400.   In that same photo of the EVM, you can see the LVDS signals route through a set of four resistor packs RN3, RN4, RN5, RN6 on their way to the LVDS connector J10.   The LVDS clock is on pins 3,4 to 5,6 of the resistor pack RN4.  This is a good place to probe for the LVDS clock.  I have seen cases where the resistor packs were placed on the EVM too close and would touch the next rpack, so things do happen, but all EVMs are tested before they go out the door. 

Please check for supply voltages and clock signals if you can, and check for the EVM set up for the proper mode of operation.     The web page for the EVM also has a zip file of the design of the EVM, so a pdf of the schematics are there if that helps.

Regards,

Richard P.