ADS52J90 Logic level of SYSREF and SYNC~

masahiko shimizu

Other Parts Discussed in Thread: ADS52J90

Hi,

My customer has questions about logic level of following pins.
Could you answer me the following questions, please?

- SYSREFP_SERDES
- SYSREFN_SERDES
- SYNCP_SERDES
- SYNCN_SERDES

Q1: Can we input signal of LVCMOS level?

Q2: If we can input signal of LVCMOS level, for design circuit, Should we use "Figure 81. Single-Ended Clock Driving Circuit" in datasheet as reference?

Best regards,
Shimizu

over 8 years ago

0 Praveen Aroul over 8 years ago

TI__Mastermind 49956 points

Hi Shimizu,

Based on the ADS52J90 datasheet, the logic levels of SYSREFP_SERDES, SYSREFN_SERDES, SYNCP_SERDES, SYNCN_SERDES signals are 1.8-V amplitude.
The signals were not tested with LVCMOS inputs.
The common mode input voltage applied on the above differential input signals was 1.2V.

0 masahiko shimizu over 8 years ago in reply to Praveen Aroul

Guru 11235 points

Hi Praveen,

Thank you for your support.
What circuit should we have for changing LVCMOS -> LVDS?

Best regards,
Shimizu

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ADS52J90 Logic level of SYSREF and SYNC~