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Dac7750/ dac8750 CRC code

Other Parts Discussed in Thread: DAC8750, DAC7750, DAC8760

Hi, I need sample code to implement CRC error checking for dac7750 or dac8750.please help me if it is implemented.

  • Somnath,

    Unfortunately I do not have any complete sample code specifically for calculating the CRC words using the polynomial implemented on DAC8760. I did find a few tools available online however which generate C source code for CRC calculators you may consider using.
  • Hi.. thanks for your reply.  Is there any sync bit or not needs to be sent before sending 32bit data.

    Do your have any link or any sample code where crc-8 ATM is implemented.

  • Somnath,

    The LATCH pin acts as the arbitration mechanism or latching mechanism of the interface. When a rising edge is seen on the LATCH pin the previous 24-bits (in non-CRC mode) or 32-bits (in CRC mode) issued on the DIN line will be latched by the serial interface. No SYNC bit or other information needs to be provided on the bus in order to utilize the CRC mode.
  • Hi Kevin,

    After little long delay I again started working on dac7750. This time the Crc is implemented and tested.

    Thanks for the guidance you provided.

    Going ahead with the development I had some observation , while reading the status register continuously in every 10 ms. Let me go with one example, I set the output  to 15ma. And started continuously reading the status bits in every 10ms. What I obsessed in this condition the output of the dac is switching back to 4ma.(initial value). Crc was disabled at this condition.

    Please provide me your views on that.

    The alarm pin I am not using.

    2. Another info needed when Crc is implemented , all frame , like reading register and writing to all register are shifted to 32 bit format or it's only applicable to writing to data register only.