I have a customer who is asking the following questions:
Can you explain the difference between Table 12 and Table 13 in the data sheet? It appears that Table 13 is referring in interleaved converters? Can you explain what is meant by this? The reason I ask is that the ADC12J2700 appears to have a single AD converter? I am not sure I understand what interleaved means in this situation. Is it just that the results are interleaved and send via different lanes depending on the decimation rate etc.?
Can you explain what the values C0S0, C1S0 etc. mean in table 12? I just need to understand what these designators stand for.
The customer is asking the following about Tables 12 and 13:
On table 12, why is each sample being sent on 8 lanes but on different converters? It seems as though the data in C0S0 would be the same as C1S0, C2S0, etc. because they have the same sample designation. Are signals like C0S0, C1S0, C2S0, etc. unique?
Table 13 makes sense because it seems like each converter sends unique samples in parallel.
What settings need to be changed to interleave the converters? (Go from the results on table 12 to table 13 or is this the same)
This questions again refers to interleaved converters and I am not sure where this comes from
How many tail bits are there for table 12 and 13? It seems like there are 4 tail bits but since N = N’ it can be said there are no tail bits.
Thanks for your help with this!
Richard Elmquist