This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADC12J2700 JESD204B Questions

Other Parts Discussed in Thread: ADC12J2700

I have a customer who is asking the following questions:

Can you explain the difference between Table 12 and Table 13 in the data sheet? It appears that Table 13 is referring in interleaved converters? Can you explain what is meant by this? The reason I ask is that the ADC12J2700 appears to have a single AD converter? I am not sure I understand what interleaved means in this situation. Is it just that the results are interleaved and send via different lanes depending on the decimation rate etc.?

Can you explain what the values C0S0, C1S0 etc. mean in table 12? I just need to understand what these designators stand for.

The customer is asking the following about Tables 12 and 13:

On table 12, why is each sample being sent on 8 lanes but on different converters? It seems as though the data in C0S0 would be the same as C1S0, C2S0, etc. because they have the same sample designation. Are signals like C0S0, C1S0, C2S0, etc. unique?

Table 13 makes sense because it seems like each converter sends unique samples in parallel. 

What settings need to be changed to interleave the converters? (Go from the results on table 12 to table 13 or is this the same)

This questions again refers to interleaved converters and I am not sure where this comes from

How many tail bits are there for table 12 and 13? It seems like there are 4 tail bits but since N = N’ it can be said there are no tail bits. 

Thanks for your help with this!

Richard Elmquist

  • Hi Richard

    Tables 12 and 13 are different ways of viewing the same data (for DDC Bypass Mode).

    Table 13 is the way the data should be considered for a single ADC converter. There are 40 samples per frame in the order shown. The data is organized in this fashion to provide the best implementation inside the ADC data transmit and FPGA data capture logic. Unfortunately when considered as a single ADC, this data format does not strictly comply with the JESD204B standard data mapping requirements.

    If we consider the device as an 8 core time-interleaved ADC as shown in Table 12, then the data mapping is compliant with the standard.

    The nomenclature of C0S0 means Converter 0 Sample 0. C1S0 means Converter 1 Sample 0, etc.

    When viewed in Table 12 we consider this as 8 time-interleaved converters, with Converter 0 sampling earliest in time, and Converter 7 sampling latest in time. Therefore the sample order in time is: C0S0, C1S0, C2S0, C3S0, C4S0, C5S0, C6S0, C7S0, C1S1, C2S1, .... C7S4 for all 40 samples in one frame. Considered this way each of the 8 sub-converters is sampling at 1/8 of the overall sample rate. When the data is interleaved the total sample rate is achieved.

    As noted above, Tables 12 and 13 are with the same device settings, nothing is changed.

    N' is used to describe the number of tail bits per sample. This is generally done in the cases where a 14 bit data sample (N=14) is padded with 2 tail bits to created a 16 bit data value (N"=16) that is transmitted.

    In the ADC12J2700 case, since we have 12 bit data, the data is already an even number of nibbles. The most efficient data packing is to group 4 tail bits at the end of each frame. The only alternative would be to add 4 tail bits to each sample using N=12 and N'=16, but this would add significant overhead to the interface. Therefore, the tail bits are not added to each sample, but are used to pad the frame period up to an even number of octets. This is compliant with the JESD204B standard, but the standard does not include a parameter to easily describe these tail bits at the end of the frame. If we try to use the N' parameter the value would be N'=12+4/5 = 12.8 since there are 4 tail bits added for every 5 samples. But N' can only be an integer, so this isn't a useful calculation. Therefore we set N=N'=12.

    Best regards,

    Jim B

  • Jim,

    Thanks for your thorough response! This can be a little confusing.

    I will let you know if the customer has any further questions.

    Thanks again.

    Richard Elmquist