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ADS8363

Paul Palamara
Prodigy 30 points

We are planning on using the ADS8363SRHBT and I have a question regarding the digital interface / timing.  I could not find a clear answer in the datasheet (but I may have missed something).  We would like to use the device in burst mode with CS tied low.  We plan to tie the CONVST and RD inputs together and toggle high-then low using a processor general purpose I/O (async) and then initiate the SPI transfer process (which will start the SPI clock, etc).

 

From what I have seen, I think it should be OK but would like some feedback before we go too far down this road—can anyone tell me if this will this work with this device?

 

Thanks.

 

  • 0
    TI__Expert 3785 points

    Hi Paul,

    If I understood the question correctly,

    1) You will be tying CONVST and RD pins together. This pair will be controlled using a GPIO.
    2) A SPI module in the processor will handle the data transfer.
    3) The SPI module and  GPIO are asynchronous.
    4) CSz will be kept low permanently.

    This operation will work. You could additionally refer to figure 31 in the data-sheet which indicates this mode of interface.

    If you could share which ADC parameter are you looking for particularly, I could suggest some alternatives.

    Regards,
    Rahul