Dear all,
the pll clock mode of dac is used. This SE-clock from the clock distributor is inputted to the pll of DAC5688. The output of the pll will be used as the internal clock of DAC. However, the pll is always lose of lock after I configurate this dac SIF registers.
Serial interface between FPGA and DAC works fine. I checked again the clock input, power supply and reset input. They all looks fine. Now I have no idea about why this pll dose not work.
Any suggestion will be appreciated!
Configuration used:
CONFIG1 0x01 0x08
CONFIG2 0x02 0x40