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Could ADC12D500RF accepts variable speed clock?

bing wang
Prodigy 10 points
Other Parts Discussed in Thread: ADC12D500RF

Hi,

I have application that the ADC sampling rate change versus time. The sampling rate change from 250MHz to 450 MHz versus time with maximum variation rate of 600MHz per micro-second. Does ADC12D500RF work in this situation?

Thanks.

Bing, 

  • 0
    TI__Mastermind 44680 points

    Hi Bing

    The ADC12D500RF can work with a variable frequency clock, as long as the following constraints are met:

    1. Minimum and maximum clock frequencies must be within the rated range for the desired mode of operation. (see Table 3.12 of the ADC12D500RF datasheet)
    2. The rate of change of clock frequency must be such that the clock input duty cycle is within the rated range of operation. (see Table 3.12 of the ADC12D500RF datasheet)
    3. This device requires calibration to achieve rated performance. To get the best compromise of performance over that frequency range, calibrate the device at the midpoint clock frequency, in this case 350 MHz.
    4. The data capture FPGA can successfully capture the ADC data with that variable DCLK and DATA rate.

    I hope this is helpful.

    Best regards,

    Jim B