Hello in our development team we have some questions regarding the Texas Instrument ADC "ADS8509IBDW". We have been encourage by Texas technical support to ask this questions here, so we hope this community can help us resolve this questions. Thanks in advance!
Questions regarding speed:
- The datasheet says that the throughput rate minimum is 250 kHz but it doesn’t tell which is the maximum sample frecuency or throughput rate allowed. We understand as throughput rate as the rate that is possible to assert the read/convert signal without interfering with the conversion process.
- Since it is possible to use a clock signal from 100kHz to 26MHz, then the maximum sample frequency that could be achieved is approximately 26Mhz/(16 serialclock cycles + some delays)?
- As it seems in the internal architecture there is a shift register where the analog signal is digitally stored when the conversion finish (Busy goes high), if this is correct then why is there a minimum sample frecuency allowed? Once the data is converted and therefore stored in the internal register it seems logical to think that you can wait as much time as you want before you start a new read/convert cycle.
Thank you very much in advance
