• State TI Thinks Resolved
  • Locked Locked
  • Replies 3 replies
  • Answers 2 answers
  • Subscribers 45 subscribers
  • Views 395 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADS8509 / Output levels at Power Down mode

user4175682
Prodigy 60 points
Other Parts Discussed in Thread: ADS8509

Hello, I cannot find any information in the datasheet about the voltage level at the output pins of the ADC ADS8509 when its PWRD pin is asserted.

We have designed a prototype that will work in a extreme environment and we need to be 100% sure that those voltage levels are either 0V either Hi-Z even if a conversion is being executed (and so the serial data is being shiftet out) when the PWRD pin is asserted.

Any help is welcome, thank you very much in advance.

 

  • 0
    TI__Expert 3785 points
    Hi,

    When PWRD is asserted, only the analog circuitry is disabled thereby reducing the power consumption of the device.
    However, result from previous conversion is maintained in the output registers.

    It is not possible to initiate new conversion in power down mode. In order to ensure the output lines remain in Hi-Z state, you could use CS pin of the device.

    I hope this helps.

    Regards,
    Rahul
  • 0 in reply to RahulVK
    Prodigy 60 points
    It appears that there is not any tri-state functionality on the ADS8509 chip as stated in this E2E post here:

    e2e.ti.com/.../75403

    If only the analog circuit is disabled I pressume that any digital output (DATA, BUSY, CLK) will mantain their state when the PWRD is asserted, so the only solution I can think of is to use a tristate buffer to enable/disable those... Or am I missing something?
  • 0 in reply to user4175682
    TI__Expert 3785 points
    Hi,

    You are right, the device pins DATA, SYNC and BUSYn do not have tri-state logic. Hence these pins will not enter tri-state mode.
    The tri-state logic only exists on DATACLK pin and is controlled by EXT/INTn pin.

    You will have to use an external buffer to implement the tri-state logic.

    Regards,
    Rahul