Dears.
Please kindly check below questions about DAC3484.
Q1. What is the reason for reset on early at Start-up Sequence.
Q2. Please provide the description for Clock divider of structure and operation which is in inner of DAC3484.
Q3. What phenomenon will be occurred when we change FIFO SYNC during it is driving.
Q4. Would you please provide more details for 33page of Datasheet as below?
Q5. Please provide Config45 bit 14(ostrtodig_sel) of function and what it means.
Thank you.
Hi Henry,
1. The hardware reset on the RESETB pin is required to ensure all the registers and internal digital logics are in the default state. This is a general good practice to ensure the device is in a known, good state before programming.
2. See section 3.2 of the app note for clock divider operation. We cannot disclose the internal detial, only the general overview.
3. If the device is operational while you change the FIFO pointer synchronization source, the FIFO pointer (both input and output) may be interrupted. The output may be corrupted and requires re-initialization of the device. The corrupted output may damage TX signal chain such as PA>
4. Please refer to section 2.2.1 of the app note:
5. This is an TI internal bypass test mode to bypass the timing logic within the DAC when capturing the OSTR. You will not need this in actual application.
-Kang
