Hi,
I'm interfacing ADS7953 with TMS320F28335's McBSP pins. I'm able to transmit data to the ADC, but I'm not able to read any values from it.
I'm configuring ADS in manual mode & scanning for each channels in step. I'm not getting any converted values on SDO. Any delay is required between each polls? When will be the data available after conversion? SCLK is ~400KHz.
Here is the sample code :
void InitMcbspaGpio(void)
{
EALLOW;
GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 2; // GPIO20 is MDXA pin
GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 2; // GPIO21 is MDRA pin
GpioCtrlRegs.GPAMUX2.bit.GPIO22 = 2; // GPIO22 is MCLKXA pin
GpioCtrlRegs.GPAMUX2.bit.GPIO24 = 0; // GPIO23 is CS pin
GpioCtrlRegs.GPAPUD.bit.GPIO20 = 0; // Enable pull-up on GPIO20 (MDXA)
GpioCtrlRegs.GPAPUD.bit.GPIO21 = 0; // Enable pull-up on GPIO21 (MDRA)
GpioCtrlRegs.GPAPUD.bit.GPIO22 = 0; // Enable pull-up on GPIO22 (MCLKXA)
GpioCtrlRegs.GPAPUD.bit.GPIO24 = 0; // Enable pull-up on GPIO24
GpioCtrlRegs.GPAQSEL2.bit.GPIO21 = 2; // Asynch input GPIO21 (MDRA)
GpioCtrlRegs.GPAQSEL2.bit.GPIO22 = 2; // Asynch input GPIO22 (MCLKXA)
GpioCtrlRegs.GPAQSEL2.bit.GPIO20 = 2; // Asynch input GPIO7 (MCLKRA) (Comment as needed)
GpioCtrlRegs.GPAQSEL2.bit.GPIO24 = 2; // Asynch input GPIO23 (MFSXA)
EDIS;
}
void InitMcbspSPI(void)
{
// McBSP-A register settings
McbspaRegs.SPCR2.all = 0x0000; // Reset FS generator, sample rate generator & transmitter
McbspaRegs.SPCR1.all = 0x0000; // Reset Receiver, Right justify word, Digital loopback dis.
McbspaRegs.PCR.all = 0x0F08; //(CLKXM=CLKRM=FSXM=FSRM= 1, FSXP = 1)
McbspaRegs.SPCR1.bit.DLB = 0;
McbspaRegs.SPCR1.bit.CLKSTP = 3; //2; // Together with CLKXP/CLKRP determines clocking scheme
McbspaRegs.PCR.bit.CLKXP = 1; //0; // CPOL = 0, CPHA = 0 rising edge no delay
McbspaRegs.PCR.bit.CLKRP = 1; //0;
McbspaRegs.RCR2.bit.RDATDLY = 01; // FSX setup time 1 in master mode. 0 for slave mode (Receive)
McbspaRegs.XCR2.bit.XDATDLY = 01; // FSX setup time 1 in master mode. 0 for slave mode (Transmit)
McbspaRegs.SPCR1.bit.RINTM = 0; //Receive interrupt on every word received on SPI
McbspaRegs.MFFINT.bit.RINT = 1; //enable receive interrupt
McbspaRegs.RCR1.bit.RWDLEN1 = 2; // 16-bit receiver buffer length
McbspaRegs.XCR1.bit.XWDLEN1 = 2; // 16-bit transmitter buffer length
McbspaRegs.SRGR2.all = 0x2000; // CLKSM=1, FPER = 1 CLKG periods
McbspaRegs.SRGR1.all = 0x000F; // Frame Width = 1 CLKG period, CLKGDV=16
McbspaRegs.SPCR2.bit.GRST = 1; // Enable the sample rate generator
delay_loop(); // Wait at least 2 SRG clock cycles
McbspaRegs.SPCR2.bit.XRST = 1; // Release TX from Reset
McbspaRegs.SPCR1.bit.RRST = 1; // Release RX from Reset
McbspaRegs.SPCR2.bit.FRST = 1; // Frame Sync Generator reset
}
void ConfigureMcBSP(void)
{
CS_McBSP_LO;
DELAY_US(1);
//first frame
McbspaRegs.DXR1.all = (ADS7953_MAN_MODE | MAN_PROG_ENABLE | MAN_25VRANGE_SEL | MAN_NORM_OP_SEL | MAN_CHAN_ADDY_SEL);
while( McbspaRegs.SPCR1.bit.RRDY == 0 );
CS_McBSP_HI;
DELAY_US(100);
CS_McBSP_LO;
DELAY_US(1);
//first frame
McbspaRegs.DXR1.all = (ADS7953_MAN_MODE | MAN_PROG_ENABLE | MAN_25VRANGE_SEL | MAN_NORM_OP_SEL | MAN_CHAN_ADDY_SEL);
while( McbspaRegs.SPCR1.bit.RRDY == 0 );
CS_McBSP_HI;
CS_McBSP_LO;
DELAY_US(1);
//first frame
McbspaRegs.DXR1.all = (ADS7953_MAN_MODE | MAN_PROG_ENABLE | MAN_25VRANGE_SEL | MAN_NORM_OP_SEL | MAN_CHAN_ADDY_SEL);
while( McbspaRegs.SPCR1.bit.RRDY == 0 );
CS_McBSP_HI;
CS_McBSP_LO;
McbspaRegs.DXR1.all = (ADS7953_MAN_MODE | MAN_PROG_ENABLE | MAN_25VRANGE_SEL | MAN_NORM_OP_SEL | MAN_CHAN_ADDY_SEL | MAN_CHANNEL_SEL_1);
while( McbspaRegs.SPCR1.bit.RRDY == 0 );
CS_McBSP_HI;
DELAY_US(100);
CS_McBSP_LO;
McbspaRegs.DXR1.all = (ADS7953_MAN_MODE | MAN_PROG_ENABLE | MAN_25VRANGE_SEL | MAN_NORM_OP_SEL | MAN_CHAN_ADDY_SEL | MAN_CHANNEL_SEL_2);
while( McbspaRegs.SPCR1.bit.RRDY == 0 );
CS_McBSP_HI;
DELAY_US(100);
CS_McBSP_LO;
McbspaRegs.DXR1.all = (ADS7953_MAN_MODE | MAN_PROG_ENABLE | MAN_25VRANGE_SEL | MAN_NORM_OP_SEL | MAN_CHAN_ADDY_SEL | MAN_CHANNEL_SEL_3);
while( McbspaRegs.SPCR1.bit.RRDY == 0 );
CS_McBSP_HI;
DELAY_US(100);
CS_McBSP_LO;
McbspaRegs.DXR1.all = (ADS7953_MAN_MODE | MAN_PROG_ENABLE | MAN_25VRANGE_SEL | MAN_NORM_OP_SEL | MAN_CHAN_ADDY_SEL | MAN_CHANNEL_SEL_4);
while( McbspaRegs.SPCR1.bit.RRDY == 0 );
CS_McBSP_HI;
}