• State TI Thinks Resolved
  • Locked Locked
  • Replies 5 replies
  • Answers 1 answer
  • Subscribers 46 subscribers
  • Views 748 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADS1282 can not output DRDY

user1102501
Prodigy 30 points
Other Parts Discussed in Thread: ADS1282

I am facing that DRDY is not output. I can not undetstand how is setting. please give me a advise. 

  • 0
    TI__Mastermind 44680 points

    Hi user1102501,

    Welcome to the TI E2E Forums!

    The ADS1282 /DRDY pin should toggle after power-on if a clock is applied and the device is not in power-down mode, as shown in figure 51:

    Note: The CLK signal should NOT be applied prior to power supplies as this figure shows.

    Check that your supply voltages are correct, the clock is present, and that the /PWDN and /RESET pins have been set high to begin the ADC conversions.

    Best Regards,
    Chris

  • 0 in reply to Christopher Hall
    Prodigy 30 points
    The supply voltage both AVDD and DVDD is 3.3V. The freqency of CLK is 3.84MHz, SCLK is 1.92MHz(equal to CLK/2). I wait 173ms (2^16/3.84Hz) after power on, and RESTE is applied Low value is kept 2clk as figure 51. But RDRY can not be Low. How is RDRY, if power on and clk is supplied at the same tme ?
  • 0 in reply to user1102501
    TI__Mastermind 44680 points

    Hi user1102501,

    AVDD ought to be a 5V supply (minimum specification is 4.75 V). Try increasing the AVDD voltage.

    Additionally, the /RESET pin needs to be set high, otherwise the device will be held in the reset state. Note that the reset signal in figure 51 is an internal signal and not the same as the /RESET pin.

    With AVDD at 3.3V and /RESET low, the device will be held in a reset stare and you will not see /DRDY toggle.

     

    Best Regards,
    Chris

  • 0 in reply to Christopher Hall
    Prodigy 30 points

    Hi Chris,

    I have set AVDD to 5V. I have confirmed that /RDRY is Low in SYNC mode. But I have not confirmed that /RDRY is low in continuous read mode. I can not understand what is setting in configulation flow.  Please give me a advices the detail of configurtiion.

    Best Regards.

    Kubo 

  • 0 in reply to user1102501
    TI__Mastermind 44680 points
    Hi Kubo,

    Have you looked at the "Configuration Guide" in the ADS1282 data sheet (on pg. 39)?
    This will give you a general start-up procedure. In step 1, I would also recommending checking the states of your GPIO pins to ensure that the SYNC, /RESET and /PWDN pins are all set high (3.3V). For now, I would recommend keeping the default register settings until you've resolved the /DRDY issue.

    You said that /DRDY is low. Do you ever see it go high?
    Typically, /DRDY should be high while the ADC is performing a conversion.

    Would it be possible for you to share some scope sceenshots of the ADS1282 CLK and GPIO signals?

    Best Regards,
    Chris