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DDC114 complementary i/o

Stefan Tauner
Prodigy 40 points
Other Parts Discussed in Thread: DDC114

hi

i could not find detailed information about the complementary inputs of the DDC11* series of ADCs.

the datasheet says "The DDC114 provides optional complementary inputs (DCLK, DIN) to help reduce digital coupling to the analog inputs. If using these inputs, connect a complementary signal to each." which i would read as "DGND level when DCLK/DIN is high and DVDD level when DCLK/DIN is low" i.e. the common ground between the sender and receiver determines the low level.

is this the correct interpretation? if so, how should one generate a complementary clock from a given ttl or cmos clock? something like the obsolete 74265 is needed and all those rs-422/485 drivers would not work(?). a simple inverter would do more harm than good because of the skew between the original true clock and the inverted signal(?)

 thanks for any input!

  • 0
    TI__Genius 14825 points

    Stefan,

    For the DIN and /DIN lines, if you are not daisy-chaining devices, then there is no need to do anything but tie DIN and /DIN to DGND as it says on page 9 of the DDC114 data sheet.  If you are chaining multiple converters, then connect DIN to DOUT of the previous device and /DIN to /DOUT of the previous device and the output signals will be synchronized, no need for external components.

    If you intend to use the DCLK and /DCLK signals, then I agree, creating a skew between the lines could do more harm than good, depending on the layout.  If you are using a microcontroller or an FPGA or a CPLD, then it should be easy to provide synchronous, differential clock outputs by using two I/O lines and no external parts.

    The DDC114 does not require that you use /DCLK to capture data - so if it is not driven to opposite-DCLK and merely tied to DGND, the device will still operate to data sheet specifications.

    Jason

  • 0 in reply to Jason Bridgmon
    Prodigy 40 points

     

    Jason Bridgmon said:

    Stefan,

    For the DIN and /DIN lines, if you are not daisy-chaining devices, then there is no need to do anything but tie DIN and /DIN to DGND as it says on page 9 of the DDC114 data sheet.  If you are chaining multiple converters, then connect DIN to DOUT of the previous device and /DIN to /DOUT of the previous device and the output signals will be synchronized, no need for external components.

    If you intend to use the DCLK and /DCLK signals, then I agree, creating a skew between the lines could do more harm than good, depending on the layout.  If you are using a microcontroller or an FPGA or a CPLD, then it should be easy to provide synchronous, differential clock outputs by using two I/O lines and no external parts.

    The DDC114 does not require that you use /DCLK to capture data - so if it is not driven to opposite-DCLK and merely tied to DGND, the device will still operate to data sheet specifications.

    Jason

    thanks for the quick answer Jason. i should have mentioned that i'm aware of that /DCLK is not needed and what /DIN and /DOUT are used for.

    i'm using an avr microcontroller and would like to use its integrated SPI function which drives the clock automatically after one writes a byte to a register. it allows to change polarity and phase but there is no way to get a complementary clock on a second pin. i could use bit banging (or not use /DCLK at all as you suggested), but i would at least like to know how i could create a low-skew complementary signal with a discrete component, if someday i have no other options :)