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ADS1178 : input full scale/transfer function /gain factor problem

Amos Oren
Prodigy 35 points
Other Parts Discussed in Thread: ADS1178

Hi, 

We are using same system configuration as described in the conversation from September 9 , 2014 . We are experiencing the same problems. We can add some moe:

We tried to measure a differential analog input +/- 210mVp/1.3 KHz (with DC of 2.5V) with CLK of 25MHz and CLKDIV at High. We got a nice signal at the right frequency but the volatge was 85mVp, we reduce the frequency to 12.5MHz and put CLKDIV al Low, we got a nice signal at the right frequency the voltage was double 170mVp, still not 210mv.

Do you have any idea 

Thanks

Amos Oren

  • 0
    TI__Guru 66516 points

    Hello Amos,

    Thanks for posting your question. Could you please provide a link to the older post you are referring to?

    The first thing I would do is verify on a scope that the differential input voltage to the ADC is as expected. This will confirm that your signal conditioning stage is not attenuating the input at all. Also, verify that the reference voltage is correct at the VREF input pins as this too can produce a gain error.

    Best Regards,

  • 0 in reply to Ryan Andrews
    Prodigy 35 points

    Hi Ryan,

    Thank You, I am referring to the link below

    e2e.ti.com/.../1296061

    I checked with Scop the Vref and the Vin and they look good.

    I would like to emphasize that I did the following:

    Vin=2.5Vdc+/-0.42Vp at 1.3KHz, Vrefp=+2.5Vdc, CLK=25MHz, CLKDIV= High and I got nice signal but amplitude of 0.085Vp

    I changed the CLK to 12.5MHz and the CLKDIV to Low with same Vin and I got double amplitude, 0.170Vp

  • 0 in reply to Amos Oren
    Prodigy 35 points
    Hi Ryan,
    The the link came wrong
    e2e.ti.com/.../1296061
  • 0 in reply to Amos Oren
    TI__Guru 66516 points
    Thanks, Amos.

    One other question about the ADS1178 device configuration: are you operating in High-Speed or Low-Power Mode? I want to verify what the modulator sampling frequency and output data rate are for your tests. (Also, you mentioned originally that your differential input signal was +/- 210mVp, which is 420mVpp; however, your last post says +/-420mVp - is that a typo?)

    It's strange to me that the gain error is changing so much with the data rate. It may be that the input the ADC has more time to settle when you slow down the clock, bringing you closer to the expected amplitude. This is usually not an issue, however, unless you have an input driver with very low bandwidth or a very large R-C network at the ADC inputs. Would mind sharing the input signal chain portion of your schematic? Also, can you provide the raw data for each configuration?

    Best Regards,